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| ICs for Communications Digital Answering Machine SAM PSB 2168 Version 2.1 Data Sheet 11.97 DS 1 PSB 2168 Revision History: Previous Version: Page Page (in previous (in new Version) Version) Current Version: 11.97 Preliminary Data Sheet 09.97 Subjects (major changes since last revision) Index added For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide: see our webpage at http://www.siemens.de/Semiconductor/address/address.htm. Edition 11.97 Published by Siemens AG, HL TS, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PSB 2168 1 1.1 1.2 1.3 1.4 1.5 1.6 1.6.1 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.7 2.1.8 2.1.9 2.1.10 2.1.11 2.1.12 2.1.13 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.4 2.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Stand-Alone Answering Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Line Echo Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 DTMF Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CNG Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Alert Tone Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CPT Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Caller ID Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DTMF Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Speech Coder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Speech Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Universal Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Automatic Gain Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 File Definition and Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 User Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 High Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . .48 Low Level Memory Management Commands . . . . . . . . . . . . . . . . . . . . . .56 Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Special Notes on File Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 SPS Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Reset and Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Auxiliary Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3 11.97 Semiconductor Group PSB 2168 2.4.2 2.4.3 2.4.4 2.4.5 3 3.1 3.2 3.3 3.3.1 3.3.2 4 4.1 4.2 4.3 5 SSDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Auxiliary Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Hardware Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Read/Write Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Register Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. DigiTapeTM, MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG. Semiconductor Group 4 11.97 PSB 2168 List of Figures General Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Page 12 16 17 18 19 20 Pin Configuration of PSB 2168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol of PSB 2168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram of PSB 2168 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Featurephone with Answering Machine for ISDN Terminal . . . . . . . . . . . Stand-Alone Answering Machine with ARAM/EPROM . . . . . . . . . . . . . . Stand-Alone Answering Machine with Flash Memory . . . . . . . . . . . . . . . Functional Units Figure 7: Functional Units - Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 8: Functional Units - Recording a Phone Conversation . . . . . . . . . . . . . . . . Figure 9: Line Echo Cancellation Unit - Block Diagram. . . . . . . . . . . . . . . . . . . . . . Figure 10: DTMF Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11: CNG Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12: Alert Tone Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13: CPT Detector - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14: CPT Detector - Cooked Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15: Caller ID Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16: DTMF Generator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 17: Speech Coder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18: Speech Decoder - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19: Digital Interface - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20: Universal Attenuator - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21: Automatic Gain Control Unit - Block Diagram . . . . . . . . . . . . . . . . . . . . . Figure 22: Automatic Gain Control Unit - Steady State Characteristic . . . . . . . . . . . Figure 23: Equalizer - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Management Figure 24: Memory Management - Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25: Memory Management - Directory Structure . . . . . . . . . . . . . . . . . . . . . . . Figure 26: Audio File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27: Binary File Organization - Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28: Phrase File Organization - Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 23 24 26 27 28 29 29 31 33 34 36 37 39 40 40 42 44 44 45 45 46 Miscellaneous Figure 29: Operation Modes - State Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Interfaces Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: IOM(R)-2 Interface - Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface - Frame Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface - Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . IOM(R)-2 Interface - Double Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . SSDI Interface - Transmitter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 66 67 67 68 70 Semiconductor Group 11.97 PSB 2168 List of Figures Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Page 71 71 72 73 73 74 74 77 78 79 79 80 80 81 82 83 83 84 84 86 SSDI Interface - Active Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . SSDI Interface - Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Read Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register Write Access or Register Read Command . . . . . ARAM/DRAM Interface - Connection Diagram. . . . . . . . . . . . . . . . . . . . . ARAM/DRAM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . ARAM/DRAM Interface - Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . ARAM/DRAM Interface - Refresh Cycle Timing . . . . . . . . . . . . . . . . . . . . EPROM Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Interface - Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface - Connection Diagram . . . . . . . . . . . . . . . . . . . . Flash Memory Interface - Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface - Command Write. . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface - Address Write . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface - Data Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Interface - Data Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics Figure 55: Input/Output Waveforms for AC-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Timing Diagrams Figure 56: Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 57: SSDI/IOM(R)-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . Figure 58: SSDI/IOM(R)-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . Figure 59: SSDI Interface - Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 60: Serial Control Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 61: Clock Master Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 62: Memory Interface - DRAM Read Access . . . . . . . . . . . . . . . . . . . . . . . . Figure 63: Memory Interface - DRAM Write Access . . . . . . . . . . . . . . . . . . . . . . . . Figure 64: Memory Interface - DRAM Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . Figure 65: Memory Interface - EPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 66: Memory Interface - Samsung Command Write . . . . . . . . . . . . . . . . . . . Figure 67: Memory Interface - Samsung Address Write . . . . . . . . . . . . . . . . . . . . . Figure 68: Memory Interface - Samsung Data Write . . . . . . . . . . . . . . . . . . . . . . . . Figure 69: Memory Interface - Samsung Data Read . . . . . . . . . . . . . . . . . . . . . . . . Figure 70: Auxiliary Parallel Port - Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . Figure 71: Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 167 167 169 170 171 172 173 174 175 176 177 178 179 180 181 Semiconductor Group 6 11.97 PSB 2168 List of Tables General Table 1: Page Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Functional Units Table 2: Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 3: Line Echo Cancellation Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Table 4: DTMF Detector Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 5: DTMF Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 6: DTMF Detector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 7: CNG Detector Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 8: CNG Detector Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Table 9: Alert Tone Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 10: Alert Tone Detector Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 11: CPT Detector Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 12: CPT Detector Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 13: Caller ID Decoder Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 14: Caller ID Decoder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 15: Caller ID Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 16: DTMF Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 17: Speech Coder Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Table 18: Speech Coder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Table 19: Speech Decoder Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Table 20: Digital Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 21: Universal Attenuator Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 22: Automatic Gain Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 23: Equalizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Memory Management - General Table 24: Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 25: Memory Management Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Table 26: Memory Management Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Memory Management - Commands Table 27: Initialize Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 28: Initialize Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 29: Activate Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 30: Activate Memory Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 31: Activate Memory Result Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 32: Open File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 33: Open Next Free File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 34: Open Next Free File Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 35: Seek Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 36: Cut File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Semiconductor Group 7 11.97 PSB 2168 Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Compress File Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Memory Status Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Memory Status Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Garbage Collection Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Access File Descriptor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Access File Descriptor Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Read Data Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Read Data Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Write Data Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Set Address Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 DMA Read Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 DMA Read Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 DMA Write Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Block Erase Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Miscellaneous Table 52: Real Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 53: SPS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 54: Power Down Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Table 55: Interrupt Source Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Table 56: Hardware Configuration Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Table 57: Auxiliary Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Table 58: Dependencies of Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Table 59: File Command Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Interfaces Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: SSDI vs. IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 IOM(R)-2 Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 SSDI Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Command Words for Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Address Field W for Configuration Register Write . . . . . . . . . . . . . . . . . . .75 Address Field R for Configuration Register Read . . . . . . . . . . . . . . . . . . .75 Supported Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Address Line Usage (ARAM/DRAM Mode) . . . . . . . . . . . . . . . . . . . . . . . .78 Refresh Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Address Line Usage (Samsung Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Flash Memory Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Static Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Multiplex Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Semiconductor Group 8 11.97 PSB 2168 Electrical Characteristics Table 74: Status Register Update Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Semiconductor Group 9 11.97 PSB 2168 Overview 1 General General Overview The PSB 2168 provides a solution for an embedded answering in an IOM(R)-2 based system. The chip features recording by DigiTapeTM, a family of high performance algorithms. Messages recorded with DigiTapeTM can be played back with variable speed without pitch alteration. Messages recorded with a higher bitrate can be converted into messages with a lower bitrate arbitrarily. Current members of DigiTape (TM) span the range from 3.3 kbit/s to 10.3 kbit/s. Furthermore the PSB 2168, V2.1 has a a caller ID decoder, DTMF recognition and generation and call progress tone detection. The frequency response of cheap microphones or loudspeakers can be corrected by a programmable equalizer. Messages and user data can be stored in ARAM/DRAM or flash memory which can be directly connected to the PSB 2168. The PSB 2168 also supports a voice prompt EPROM for fixed announcements. The PSB 2168 provides an IOM(R)-2 compatible interface with two channels for speech data. Alternatively to the IOM(R)-2 compatible interface the PSB 2168 supports a simple serial data interface (SSDI) with separate strobe signals for each direction (linear PCM data, one channel). The chip is programmed by a simple four wire serial control interface and can inform the microcontroller of new events by an interrupt signal. For data retention the PSB 2168 supports a power down mode where only the real time clock and the memory refresh (in case of ARAM/DRAM) are operational. The PSB 2168 supports interface pins to +5 V levels. Semiconductor Group 10 11.97 Digital Answering Machine SAM PSB 2168 Version 2.1 CMOS 1.1 Features Digital Functions * * * * * * * * * * * * * * * High performance recording by DigiTapeTM Selectable compression rate (3.3 kbit/s, 10.3 kbit/s) Variable playback speed Support for ARAM or Flash Memory Optional voice prompt EPROM DTMF generation and detection Call progress tone detection Caller ID recognition Direct memory access Real time clock Equalizer Automatic gain control Automatic timestamp Auxiliary parallel port Ultra low power refresh mode P-MQFP-80 General Features * SSDI/IOM(R)-2 compatible interface * Serial control interface for programming * Master clock generation for common codecs Type PSB 2168 Semiconductor Group Package P-MQFP-80 11 11.97 PSB 2168 Overview 1.2 Pin Configuration (top view) 60 VDD MA4 MA5 MA6 MA7 VSS VDD MA8 MA9 MA10 MA11 VSS VDD MA12 MA13 MA14 MA15 VSS RST VDDP 61 VSS VSS VDD VSS RO MA3 MA2 MA1 MA0 MD7 MD6 VDD VSS MD5 MD4 MD3 MD2 MD1 MD0 VDDP 50 41 40 VSS VDD SPS1 SPS0 CAS1/FCS CAS0/ALE RAS/FOE VPRD/FCLE W/FWE FRDY VSS VDD DRST DXST DD/DR DU/DX DCL FSC VSS VDD SAM 70 PSB 2168 30 80 1 10 20 21 Figure 1 Pin Configuration of PSB 2168 Semiconductor Group VDDA XTAL1 XTAL2 VSSA OSC1 OSC2 VDD CLK VSS INT SCLK SDX SDR CS VDD VSS AFEFS AFECLK RO VSS 12 11.97 PSB 2168 Overview 1.3 Table 1 Pin No. P-MQFP-80 Pin Definitions and Functions Pin Definitions and Functions Symbol Dir. Reset Function Power supply (5V 10 %) Power supply for the interface. Power supply (3.0 V - 3.6 V) Power supply for logic. 41, 80 VDDP 7, 15, 21, VDD 29, 39, 49, 58, 61, 67, 73 1 4 VDDA VSSA - - Power supply (3.0 V - 3.6 V) Power supply for clock generator. Power supply (0 V) Ground for clock generator. Power supply (0 V) Ground for logic and interface. 9, 16,20, VSS 22, 30, 40, 48, 57, 59, 60, 78, 66, 72 17 AFEFS O L Analog Frontend Frame Sync: 8 kHz frame synchronization signal for the analog front end. Analog Frontend Clock: Clock signal for the analog front end. Reset: Active high reset signal. Data Frame Synchronization: 8 kHz frame synchronization signal (IOM(R)-2 and SSDI mode). Data Clock: Data Clock of the serial data interface. IOM(R)-2 Compatible Mode: Receive data from IOM(R)-2 controlling device. SSDI Mode: Receive data of the strobed serial data interface. 18 79 23 AFECLK O RST FSC I I L - 24 26 DCL DD/DR I I/OD I - Semiconductor Group 13 11.97 PSB 2168 Overview Table 1 25 Pin Definitions and Functions DU/DX I/OD O/ OD 27 28 14 11 13 12 10 52 53 54 55 62 63 64 65 68 69 70 71 74 75 76 77 DXST DRST CS SCLK SDR SDX INT MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 O I I I I O/ OD O/ OD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O L H H L1) L L L L L L L L L L L L L L L IOM(R)-2 Compatible Mode: Transmit data to IOM(R)-2 controlling device. SSDI Mode: Transmit data of the strobed serial data interface. DX Strobe: Strobe for DX in SSDI interface mode. DR Strobe: Strobe for DR in SSDI interface mode. Chip Select: Select signal of the serial control interface (SCI). Serial Clock: Clock signal of the serial control interface (SCI). Serial Data Receive: Data input of the serial control interface (SCI). Serial Data Transmit: Data Output of the serial control interface (SCI). Interrupt New status available. Memory Address 0-15: Multiplexed address outputs for ARAM, DRAM access. Non-multiplexed address outputs for voice prompt EPROM. Auxiliary Parallel Port: General purpose I/O. Semiconductor Group 14 11.97 PSB 2168 Overview Table 1 42 43 44 45 46 47 50 51 35 Pin Definitions and Functions MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 CAS0/ ALE CAS1/ FCS RAS/ FOE I/O I/O I/O I/O I/O I/O I/O I/O O H2) Memory Data 0-7: Memory (ARAM, DRAM, Flash Memory, EPROM) data bus. ARAM, DRAM: Column address strobe for memory bank 0 or 1. Flash Memory: Address Latch Enable for address lines A16-A23. Chip select signal for Flash Memory 36 O 34 O H2) ARAM, DRAM: Row address strobe for both memory banks. Flash Memory: Output enable signal for Flash Memory. ARAM, DRAM: Read signal for voice prompt EPROM. Flash Memory: Command latch enable for Flash Memory. ARAM, DRAM: Write signal for all memory banks. Flash Memory: Write signal for Flash Memory. Flash Memory Ready Input for Ready/Busy signal of Flash Memory Auxiliary Oscillator: Oscillator loop for 32.768 kHz crystal. Alternative AFECLK Source 13,824 MHz Oscillator: XTAL1: External clock or input of oscillator loop. XTAL2: output of oscillator loop for crystal. 33 VPRD/ FCLE O H2) 32 W/FWE O H2) 31 5 6 8 2 3 FRDY OSC1 OSC2 CLK XTAL1 XTAL2 I I O I I O Z Z Semiconductor Group 15 11.97 PSB 2168 Overview Table 1 37 38 19, 56 1) 2) Pin Definitions and Functions SPS0 SPS1 RO O O O L L Multipurpose Outputs: General purpose, address lines or status Reserved Output Must be left open. These lines are driven low with 125 A until the mode (address lines or auxiliary port) is defined. These lines are driven high with 70 A during reset. 1.4 1 Logic Symbol RST INT SDX SDR SCLK CS OSC1 OSC2 XTAL1 XTAL2 DXST DRST DU/DX DD/DR DCL FSC SCI PSB 2168 VDD VDDA VSS CAS0/ CAS1/ MA0-MA15 MD0-MD7 ALE FCS RAS/ FOE W/ FWE IOM(R)-2 SDI VPRD/ FCLE FRDY Memory Figure 2 Logic Symbol of PSB 2168 Semiconductor Group 16 11.97 PSB 2168 Overview 1.5 Functional Block Diagram RST OSC1 OSC2 XTAL1 XTAL2 Reset and Timing Unit DXST DRST DU/DX DD/DR DCL FSC Data Interface INT SDX DSP Control Interface SDR SCLK CS Memory Interface FRDY MA0-MA15 MD0-MD7 CAS0/ CAS1/ ALE FCS RAS/ FOE W/ FWE VPRD/ FCLE Figure 3 Block Diagram of PSB 2168 1.6 System Integration The integration into an ISDN terminal is shown in figure 4. All voice data is transferred by the IOM(R)-2 compatible interface. The PSB 2168 is programmed by the SCI interface. The PSB 2163 is programmed by the IOM(R)-2 interface. The microcontroller can access the memory attached to the PSB 2168. This is useful for storing system parameters or phonebook entries. Semiconductor Group 17 11.97 PSB 2168 Overview IOM(R)-2 PSB 2163 Flash PSB 2168 PSB 2186 S0-BUS 077-3445 Power Controller Microcontroller PEB 2023 Figure 4 Featurephone with Answering Machine for ISDN Terminal Semiconductor Group 18 11.97 PSB 2168 Overview 1.6.1 Stand-Alone Answering Machine The PSB 2168 can also be used in conjunction with a simple codec for a stand-alone answering machine (figure 5). In this application the PSB 2168 generates the necessary clocks for the simple codec at the pins AFECLK and AFEFS. Therefore the simple codec can be connected without further glue logic. AFECLK CLK DCL DR ARAM analog mux/amp simple codec TX TR FS PSB 2168 DX FSC AFEFS Voice Prompt EPROM tip/ ring 077-3445 Microcontroller line Figure 5 Stand-Alone Answering Machine with ARAM/EPROM Semiconductor Group 19 11.97 PSB 2168 Overview Furthermore the PSB 2168 can be used to scan the keyboard and drive the display if instead of ARAM/DRAM and EPROM flash memory devices (SAMSUNG mode) are used for storage (figure 6). IOM(R)-2 simple codec analog mux/amp PSB 2168 Flash AFE tip/ ring 077-3445 Microcontroller line Figure 6 Stand-Alone Answering Machine with Flash Memory In either case all features of the PSB 2168 can be used (e.g. caller id). Semiconductor Group 20 11.97 PSB 2168 Functional Description 2 Functional Units Functional Units Functional Description The PSB 2168 contains several functional units that can be combined with almost no restrictions to perform a given task. Figure 7 gives an overview of the important functional units. SSDI/IOM(R)-2 Channel 1 IOM(R)-2 Channel 2 S6 S8 S5 I1 I2 I3 S7 I1 I2 I3 S13 Speech Decoder Memory Speech Coder I1 I1 DTMF Generator Universal Attenuator I1 I2 I1 I2 I2 I1 Line Echo Canceller AGC Equalizer S9 S10 I1 CNG Detector S14 I1 Alert Tone Detector S15 I1 CPT Detector S16 S17 I1 CID Decoder S18 I1 DTMF Detector SCI signal summation: I1 I2 I3 signal sources: S5,...,S18 Figure 7 Functional Units - Overview 21 11.97 Semiconductor Group PSB 2168 Functional Description Each unit has one or more signal inputs (denoted by I). Most units have at least one signal output (denoted by S). Any input I can be connected to any signal output S. In addition to the signals shown in figure 7 there is also the signal S0 (silence), which is useful at signal summation points. Table 2 lists the available signals within the PSB 2168 according to their reference points. Table 2 Signal S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 Signal Summary Description Silence Reserved Reserved Reserved Reserved Serial interface input, channel 1 Serial interface output, channel 1 Serial interface input, channel 2 Serial interface output, channel 2 DTMF generator output DTMF generator auxiliary output Reserved Reserved Speech decoder output Universal attenuator output Line echo canceller output Automatic gain control output (after gain stage) Automatic gain control output (before gain stage) Equalizer output Semiconductor Group 22 11.97 PSB 2168 Functional Description The following figures show the connections for a typical state during operation. Units that are not needed are not shown. Inputs that are not needed are connected to S0 which provides silence (denoted by 0). In figure 8 a phone conversation is currently in progress. The speech coder is used to record the signals of both parties. The alert tone detector is used to detect an alerting tone of an off-hook caller id request while the CID decoder decodes the actual data transmitted in this case. SSDI/IOM(R)-2 Channel 1 IOM(R)-2 Channel 2 S5 S7 000 000 Memory Speech coder AGC CPT detector CID decoder DTMF detector SCI Figure 8 Functional Units - Recording a Phone Conversation Semiconductor Group 23 11.97 PSB 2168 Functional Description 2.1 Functional Units In this section the functional units of the PSB 2168 are described in detail. The functional units can be individually enabled or disabled. 2.1.1 Line Echo Canceller The PSB 2168 contains an adaptive line echo cancellation unit for the cancellation of near end echoes. The unit has two modes: normal and extended. In normal mode, the maximum echo length is 4 ms. This mode is always available. In extended mode, the maximum echo length is 24 ms. Extended mode cannot be used while the speech encoder or slow playback is active. The line echo cancellation unit is especially useful in front of the various detectors (DTMF, CPT, etc.). A block diagram is shown in figure 9. I2 + S15 Adaptive Filter I1 Figure 9 Line Echo Cancellation Unit - Block Diagram The line echo canceller provides only one outgoing signal (S15) as the other outgoing signal would be identical with the input signal I1. Input I2 is usually connected to the line input while input I1 is connected to the outgoing signal. In normal mode the adaption process can be controlled by three parameters: MIN, ATT and MGN. Adaption takes only place if both of the following conditions hold: 1. I1 > MIN 2. I1 - I2 - ATT + MGN > 0 With the first condition adaption to small signals can be avoided. The second condition avoids adaption during double talk. The parameter ATT represents the echo loss provided by external circuitry. The adaption stops if the power of the received signal (I2) exceeds the power of the expected signal (I1-ATT) by more than the margin MGN. Semiconductor Group 24 11.97 PSB 2168 Functional Description Table 3 shows the registers associated with the line echo canceller. Table 3 Register LECCTL LECCTL LECCTL LECCTL LECLEV LECATT Line Echo Cancellation Unit Registers # of Bits Name Comment 1 1 5 5 15 15 EN MD I2 I1 MIN ATT MGN Line echo canceller enable Line echo canceller mode Input signal selection for I2 Input signal selection for I1 Minimal power for signal I1 Margin for double talk detection both both normal normal Relevant Mode both Externally provided attenuation (I1 to I2) normal LECMGN 15 Semiconductor Group 25 11.97 PSB 2168 Functional Description 2.1.2 DTMF Detector Figure 10 shows a block diagram of the DTMF detector. The results of the detector are available in the status register and a dedicated result register that can be read via the serial control interface (SCI) by the external controller. All sixteen standard DTMF tones are recognized. I1 DTMF Recognition SCI Figure 10 DTMF Detector - Block Diagram Table 4 to 6 show the associated registers. Table 4 DDCTL DDCTL DTMF Detector Control Register Name EN I1 Comment DTMF detector enable Input signal selection 1 5 Register # of Bits As soon as a valid DTMF tone is recognized, the status word and the DTMF tone code are updated (table 5). Table 5 DTMF Detector Results Name DTV DTC Comment DTMF code valid DTMF tone code Register # of Bits STATUS 1 DDCTL 5 DTV is set when a DTMF tone is recognized and reset when no DTMF tone is recognized or the detector is disabled. The code for the DTMF tone is placed into the register DDCTL. The registers DDTW and DDLEV hold parameters for detection (table 6). Table 6 Register DDTW DDLEV DTMF Detector Parameters # of Bits 15 6 Name TWIST MIN Comment Twist for DTMF recognition Minimum signal level to detect DTMF tones Semiconductor Group 26 11.97 PSB 2168 Functional Description 2.1.3 CNG Detector The calling tone (CNG) detector can detect the standard calling tones of fax machines or modems. This helps to distinguish voice messages from data transfers. The result of the detector is available in the status register that can be read via the serial control interface (SCI) by the external controller. The CNG detector consists of two band-pass filters with fixed center frequency of 1100 Hz and 1300 Hz. CNG Detector I1 1100 Hz 1300 Hz SCI Figure 11 CNG Detector - Block Diagram Table 7 shows the available parameters. Table 7 Register CNGCTL CNGCTL CNGLEV CNGBT CNGRES CNG Detector Registers # of Bits 1 5 16 16 16 Name EN I1 MIN TIME RES Comment CNG detector enable Input signal selection Minimum signal level Minimum time of signal burst Input signal resolution Both the programmed minimum time and the minimum signal level must be exceeded for a valid CNG tone. Furthermore the input signal resolution can be reduced by the RES parameter. This can be useful in a noisy environment at low signal levels although the accuracy of the detection decreases. As soon as a valid tone is recognized, the status word of the PSB 2168 is updated. The status bits are defined as follows: Table 8 CNG Detector Result Name CNG Comment Fax/Modem calling tone detected Register # of Bits STATUS 1 Semiconductor Group 27 11.97 PSB 2168 Functional Description 2.1.4 Alert Tone Detector The alert tone detector can detect the standard alert tones (2130 Hz and 2750 Hz) for caller id protocols. The results of the detector are available in the status register and the dedicated register ATDCTL0 that can be read via the serial control interface (SCI) by the external controller. Alert Tone I1 Detector SCI Figure 12 Alert Tone Detector - Block Diagram Table 9 Register ATDCTL0 ATDCTL0 ATDCTL1 ATDCTL1 ATDCTL1 Alert Tone Detector Registers # of Bits 1 5 1 1 8 Name EN I1 MD DEV MIN Comment Alert Tone Detector Enable Input signal selection Detection of dual tones or single tones Maximum deviation (0.5% or 1.1%) Minimum signal level to detect alert tones As soon as a valid alert tone is recognized, the status word of the PSB 2168 and the code for the detected combination of alert tones are updated (table 10). Table 10 Register STATUS ATDCTL0 Alert Tone Detector Results # of Bits Name 1 2 ATV ATC Comment Alert tone detected Alert tone code Semiconductor Group 28 11.97 PSB 2168 Functional Description 2.1.5 CPT Detector The selected signal is monitored continuously for a call progress tone. The CPT detector consists of a band-pass and an optional timing checker (figure 13). Band-pass I1 300-640 Hz SCI (Status) Timing Checker Figure 13 CPT Detector - Block Diagram The CPT detector can be used in two modes: raw and cooked. In raw mode, the occurrence of a signal within the frequency range, time and energy limits is directly reported. The timing checker is bypassed and therefore the PSB 2168 does not interpret the length or interval of the signal. In cooked mode, the number and duration of signal bursts are interpreted by the timing checker. A signal burst followed by a gap is called a cycle. Cooked mode requires a minimum of two cycles. The CPT flag is set with the first burst after the programmed number of cycles has been detected. The CPT flag remains set until the unit is disabled, even if the conditions are not met anymore. In this mode the CPT is modelled as a sequence of identical bursts separated by gaps with identical length. The PSB 2168 can be programmed to accept a range for both the burst and the gap. It is also possible to specify a maximum aberration of two consecutive bursts and gaps. Figure 14 shows the parameters for a single cycle (burst and gap). tBmax tBmin tGmin tGmax Figure 14 CPT Detector - Cooked Mode The status bit is defined as follows: Semiconductor Group 29 11.97 PSB 2168 Functional Description Table 11 CPT Detector Result Name CPT Comment CP tone currently detected [340 Hz; 640 Hz] Register # of Bits STATUS 1 CPT is not affected by reading the status word. It is automatically reset when the unit is disabled. Table 12 shows the control register for the CPT detector. Table 12 Register CPTCTL CPTCTL CPTCTL CPTMN CPTMN CPTMX CPTMX CPTDT CPTDT CPTTR CPTTR CPTTR CPT Detector Registers # of Bits Name 1 1 5 8 8 8 8 8 8 3 8 4 EN MD I1 MINB MING MAXB MAXG DIFB DIFG NUM MIN SN Comment Unit enable Mode (cooked, raw) Input signal selection Minimum time of a signal burst (tBmin) Minimum time of a signal gap (tGmin) Maximum time of a signal burst (tBmax) Maximum time of a signal gap (tGmax) Maximum difference between consecutive bursts Maximum difference between consecutive gaps Number of cycles (cooked mode), 0 (raw mode) Minimum signal level to detect tones Minimal signal-to-noise ratio If any condition is violated during a sequence of cycles the timing checker is reset and restarts with the next valid burst. Note: In cooked mode CPT is set with the first burst after the programmed number of cycles has been detected. Note: The number of cycles must be set to zero in raw mode. Semiconductor Group 30 11.97 PSB 2168 Functional Description 2.1.6 Caller ID Decoder The caller ID decoder is basically a 1200 baud modem (FSK, demodulation only). The bit stream is formatted by a subsequent UART and the data is available in a data register along with status information (figure 15). I1 FSK demod. (Bellcore, V.23) UART SCI (Status, Data) Figure 15 Caller ID Decoder - Block Diagram The FSK demodulator supports two modes according to table 13. The appropriate mode is detected automatically. Table 13 Mode 1 2 Caller ID Decoder Modes Mark (Hz) 1200 1300 Space (Hz) 2200 2100 Comment Bellcore V.23 The CID decoder does not interpret the data received. Each byte received is placed into the CIDCTL register (table 15). The status byte of the PSB 2168 is updated (table 14). Table 14 Caller ID Decoder Status Name CIA CD Comment CID byte received Carrier Detected Register # of Bits STATUS 1 STATUS 1 CIA and CD are cleared when the unit is disabled. In addition, CIA is cleared when CIDCTL0 is read. Table 15 Register CIDCTL0 CIDCTL0 CIDCTL0 Caller ID Decoder Registers # of Bits Name 1 5 8 EN I1 DATA Comment Unit enable Input signal selection Last CID data byte received Semiconductor Group 31 11.97 PSB 2168 Functional Description Table 15 Register CIDCTL1 CIDCTL1 CIDCTL1 Caller ID Decoder Registers # of Bits Name 5 6 5 NMSS NMB MIN Comment Number of mark/space sequences necessary for successful detection of carrier detect Number of mark bits necessary before space of first byte after carrier detect Minimum signal level for CID detection When the CID unit is enabled, it first waits for a channel seizure signal consisting of a series of alternating space and mark signals. The number of spaces and marks that have to be received without errors before the PSB 2168 reports a carrier detect by setting status bit CD can be programmed. Channel seizure must be followed by at least 16 continuous mark signals. The first space signal detected is then regarded as the start bit of the first message byte. The interpretation of the data, including message type, length and checksum is completely left to the controller. The CID unit should be disabled as soon as the complete information has been received as it cannot detect the end of the transmission by itself. Note: Some caller ID mechanism may require additional external components for DC decoupling. These tasks must be handled by the controller. Note: The controller is responsible for selecting and storing parts of the CID as needed. Semiconductor Group 32 11.97 PSB 2168 Functional Description 2.1.7 DTMF Generator The DTMF generator can generate single or dual tones with programmable frequency and gain. This unit is primarily used to generate the common DTMF tones but can also be used for signalling or other user defined tones. A block diagram is shown in figure 16. f1 generator gain1 att1 S9 f2 generator gain2 att2 S10 Figure 16 DTMF Generator - Block Diagram Both generators and amplifiers are identical. There are two modes for programming the generators, cooked mode and raw mode. In cooked mode, the standard DTMF frequencies are generated by programming a single 4 bit code. In raw mode, the frequency of each generator/amplifier can be programmed individually by a separate register. The unit has two outputs which provide the same signal but with individually programmable attenuation. Table 16 shows the parameters of this unit. Table 16 DGCTL DGCTL DGCTL DGF1 DGF2 DGL DGL DGATT DGATT DTMF Generator Registers Name EN MD DTC FRQ1 FRQ2 LEV1 LEV2 ATT1 ATT2 Comment Enable for generators Mode (cooked/raw) DTMF code (cooked mode) Frequency of generator 1 Frequency of generator 2 Level of signal for generator 1 Level of signal for generator 2 Attenuation of S9 Attenuation of S10 1 1 4 15 15 7 7 8 8 Register # of Bits Note: DGF1 and DGF2 are undefined when cooked mode is used and must not be written. Semiconductor Group 33 11.97 PSB 2168 Functional Description 2.1.8 Speech Coder The speech coder (figure 17) has two input signals I1 and I2. The first signal (I1) is fed to the coder while the second signal (I2) is used as a reference signal for voice controlled recording. The signal I1 can be coded by either a High Quality coder or a Long Play coder. I1 MIN HQ 10300 bit/s Memory I2 LP LP 3300 bit/s Figure 17 Speech Coder - Block Diagram In High Quality the output data stream runs at a fixed rate of 10300 bit/s and provides excellent speech quality. In Long Play mode, the output data stream is further reduced to an average of 3300 bit/s while still maintaining good quality. Data is written starting at the current file pointer and the file pointer is advanced as needed. In case of any memory error (e.g. memory full) a file error is indicated and the coder is disabled. The controller must subsequently close the file. The coder can be switched on the fly. However, it may take up to 60 ms until the switch is executed. The controller must therefore wait for at least this time until issuing another command that relies on the mode switch. No audio data is lost during switching. The signal I2 is first filtered by a low pass LP1 with programmable time constant and then compared to a reference level MIN. If the filtered signal exceeds MIN, then the status bit SD (table 17) is set immediately. If the filtered signal has been smaller than MIN for a programmable time TIME then the status bit SD is reset. The coder can be enabled in permanent mode or in voice recognition mode. In permanent mode, the coder starts immediately and compresses all input data continuously. The current state of the status bit SD does not affect the coder. In voice recognition mode, the coder is automatically started on the first transition of the status bit from 0 to 1. Once the coder has started it remains active until disabled. Table 17 Speech Coder Status Name SD Comment Speech detected Register # of Bits STATUS 1 Semiconductor Group 34 11.97 PSB 2168 Functional Description The operation of the speech coder is defined according to table 18. Table 18 SCCTL SCCTL SCCTL SCCTL SCCTL SCCT2 SCCT2 SCCT3 Speech Coder Registers Name EN HQ VC I1 I2 MIN TIME LP Comment Enable speech coder High quality mode Voice controlled recording Input signal 1 selection Input signal 2 selection Minimal signal level for speech detection Minimum time for reset of SD Time constant for low-pass 1 1 1 5 5 8 8 8 Register # of Bits Note: The peak data rate in LP mode is 4800 bit/s. Note: Both HQ and LP mode will not produce identical bit streams after a coding/ decoding cycle. Semiconductor Group 35 11.97 PSB 2168 Functional Description 2.1.9 Speech Decoder The speech decoder (figure 18) decompresses the data previously coded by the speech coder unit and delivers a standard 128 kbit/s data stream. HQ 10300 bit/s Memory S13 LP 3300 bit/s Figure 18 Speech Decoder - Block Diagram The decoder supports fast (1.5 and 2.0 times) and slow (0.5 times) motion independent of the selected quality. The decoder requests input data as needed at a variable rate. Table 19 shows the signal and mode selection for the speech decoder. Table 19 SDCTL SDCTL Speech Decoder Registers Name EN SPEED Comment Enable speech decoder Selection of playback speed 1 2 Register # of Bits Data reading starts at the location of the current file pointer. The file pointer is updated during speech decoding. If the end of the file is reached, the decoder is automatically disabled. The PSB 2168 automatically resets SDCTL:EN at this point. Semiconductor Group 36 11.97 PSB 2168 Functional Description 2.1.10 Digital Interface There are two almost identical interfaces at the digital side as shown in figure 19. The only difference between these two interfaces is that only channel 1 supports the SSDI mode. Channel 1 (SSDI/IOM(R)-2 Interface) I1 Channel 2 (IOM(R)-2 Interface) I1 S6 I2 S8 I2 ATT1 I3 ATT2 I3 HP S5 HP S7 Figure 19 Digital Interface - Block Diagram Each outgoing signal can be the sum of two signals with no attenuation and one signal with programmable attenuation (ATT). The attenuator can be used for artificial echo if there is none externally provided (e.g. ISDN application). Each input can be passed through an optional high-pass (HP). The associated registers are shown in table 20. Table 20 IFS3 IFS3 IFS3 IFS3 IFS4 IFS4 IFS4 IFS4 Digital Interface Registers Name I1 I2 I3 HP I1 I2 I3 HP Comment Input signal 1 for S6 Input signal 2 for S6 Input signal 3 for S6 High-pass for S5 Input signal 1 for S8 Input signal 2 for S8 Input signal 3 for S8 High-pass for S7 5 5 5 1 5 5 5 1 Register # of Bits Semiconductor Group 37 11.97 PSB 2168 Functional Description Table 20 IFG5 IFG5 Digital Interface Registers Name ATT1 ATT2 Comment Attenuation for input signal I3 (Channel 1) Attenuation for input signal I3 (Channel 2) 8 8 Register # of Bits Semiconductor Group 38 11.97 PSB 2168 Functional Description 2.1.11 Universal Attenuator The PSB 2168 contains an universal attenuator that can be connected to any signal (e.g. for sidetone gain in ISDN applications). I1 UA S14 Figure 20 Universal Attenuator - Block Diagram Table 21 shows the associated register. Table 21 UA UA Universal Attenuator Registers Name ATT I1 Comment Attenuation for UA Input signal for UA 8 5 Register # of Bits Semiconductor Group 39 11.97 PSB 2168 Functional Description 2.1.12 Automatic Gain Control Unit In addition to the universal attenuator with programmable but fixed gain the PSB 2168 contains an amplifier with automatic gain control (AGC). The AGC is preceeded by a signal summation point for two input signals. One of the input signals can be attenuated. I1 AGC S16 I2 ATT S17 Figure 21 Automatic Gain Control Unit - Block Diagram Furthermore the signal after the summation point is available. Besides providing a general signal summation (S16 not used) this signal is especially useful if the AGC unit provides the input signal for the speech coder. In this case S17 can be used as a reference signal for voice controlled recording. Operation of the AGC depends on a threshold level defined by the parameter COM (value relative to the maximum PCM-value). The bold line in Figure 22 depicts the steady-state output level of the AGC as a function of the input level. AGC input level -20 dB -10 dB max. PCM Example: COM = -30 dB AG_GAIN = 15 dB AG_ATT = 20 dB -10 dB AG_ATT -20 dB COM AGC output level AG_GAIN Figure 22 Automatic Gain Control Unit - Steady State Characteristic Semiconductor Group 40 11.97 PSB 2168 Functional Description The regulation speed is controlled by SPEEDH for signal amplitudes above the threshold and SPEEDL for amplitudes below. Usually SPEEDH will be chosen to be at least 10 times faster than SPEEDL. The AGC reacts faster for higher values of SPEEDH (SPEEDL). The current gain/attenuation of the AGC can be read at any time. An additional low pass with time constant LP is provided to avoid an immediate response of the AGC to very short signal bursts. Furthermore the AGC contains a comparator that starts and stops the gain regulation. The signal after the summation point (S17) is filtered by a peak detector with time constant DEC for decay. Then the signal is compared to a programmable limit LIM. Regulation takes only place when the filtered signal exceeds the limit. Table 22 shows the associated registers. Table 22 Automatic Gain Control Registers Name EN I1 I2 ATT AG_INIT COM SPEEDL SPEEDH AG_ATT AG_GAIN DEC LIM LP Comment Enable Input signal 1 for AGC Input signal 2 for AGC Attenuation for I2 Initial AGC gain/attenuation Compare level rel. to max. PCM-value Change rate for lower levels Change rate for higher level Attenuation range Gain range Peak detector time constant Comparator minimal signal level AGC low pass time constant Register # of Bits AGCCTL 1 AGCCTL 5 AGCCTL 5 AGCATT 15 AGC1 AGC1 AGC2 AGC2 AGC3 AGC3 AGC4 AGC4 AGC5 8 8 8 8 8 7 7 8 7 Semiconductor Group 41 11.97 PSB 2168 Functional Description 2.1.13 Equalizer The PSB 2168 also provides an equalizer that can be inserted into any signal path. The main application for the equalizer is the adaption to the frequency characteristics of the microphone, transducer or loudspeaker. The equalizer consists of an IIR filter followed by an FIR filter as shown in figure 23. I z-1 z-1 z-1 z-1 z-1 z-1 IIR A1 A2 A9 B9 B2 C1 z-1 z-1 z-1 FIR D1 D2 D17 S18 C2 Figure 23 Equalizer - Block Diagram The coefficients A1-A9, B2-B9 and C1 belong to the IIR filter, the coefficients D1-D17 and C2 belong to the FIR filter. Table 23 shows the registers associated with the equalizer. Table 23 FCFCTL FCFCTL FCFCTL Equalizer Registers Name EN I ADR Comment Enable Input signal for equalizer Filter coefficient address Filter coefficient data 1 5 6 Register # of Bits FCFCOF 16 Semiconductor Group 42 11.97 PSB 2168 Functional Description Due to the multitude of coefficients the PSB 2168 uses an indirect addressing scheme for reading or writing an individual coefficient. The address of the coefficient is given by ADR and the actual value is read or written to register FCFCOF. In order to ease programming the PSB 2168 automatically increments the address ADR after each access to FCFCOF. Note: Any access to an out-of-range address automatically resets FCFCTL:ADR. Semiconductor Group 43 11.97 PSB 2168 Functional Description 2.2 Memory Management Memory Management - General Memory Management This section describes the memory management provided by the PSB 2168. As figure 24 shows, three units can access the external memory. During recording, the speech coder can write compressed speech data into the external memory. For playback, the speech decoder reads compressed speech data from external memory. In addition, the microcontroller can directly access the memory by the SCI interface. Speech Decoder SCI Memory Speech Coder Figure 24 Memory Management - Data Flow The memory is organized as a file system. For each memory space (R/W-memory and voice prompt memory) the PSB 2168 maintains a directory with 255 file descriptors (figure 25). directory file descriptor 1 file descriptor (R/W) length (0-65535) user data (16 bits) file descriptor n RTC1 (16 bits) RTC2 (16 bits) file descriptor 255 Figure 25 Memory Management - Directory Structure The directories must be created after each power failure for volatile R/W-memory. All file descriptors are cleared (all words zero). For non-volatile memory, the directories have to Semiconductor Group 44 11.97 PSB 2168 Functional Description be created only once. If the directories already exist, the memory has just to be activated after a reset. The file descriptors are not changed in this case. All commands that access the other fields or involve a write access must not be used in voice prompt memory space. 2.2.1 File Definition and Access A file is a linear sequence of units and can be accessed in two modes: binary and audio. In binary mode, a unit is a word. In audio mode, a unit is a variable number of words representing 30 ms of uncompressed speech. A file can contain at most 65535 units. Figure 26 shows an audio file containing 100 audio units. The length of the message is therefore 3 s. 3s Hi Jack, this is Tom. Please call me back tomorrow. 0 99 Figure 26 Audio File Organization - Example Figure 27 shows a binary file of 11 words containing a phonebook (with only two entries). TO M 55 54 30 J AC K 55 58 11 544F 4D20 3535 3534 3330 004A 4143 4B20 5555 5538 3131 0 1 10 Figure 27 Binary File Organization - Example There is one special file in the voice prompt directory (referenced by file number 255) which is intended for a large number of phrases and hence has a different organization.This file exists only in the directory for the voice prompt memory. It consists of up to 2048 phrases of arbitrary individual length. The actual number of units within an individual phrase is determined during creation and cannot be altered afterwards. Phrases can be combined in any sequence without intermediate noise or gaps. Semiconductor Group 45 11.97 PSB 2168 Functional Description Figure 28 shows a phrase file containing a total of five phrases. you have messages left one two friday 0 1 4 Figure 28 Phrase File Organization - Example Before an access to a file can take place, the file must be opened with the following information: 1. memory space (messages or voice prompts) 2. file number 3. access mode These parameters remain effective until the next open command is given or, in case of the file pointer, until a file access. All other files are closed and cannot be accessed. The file with file number 0 is not a physical file. Opening this file closes all physical files. The PSB 2168 provides four registers for file access and two bits within the STATUS register. Table 24 shows these registers. Table 24 FCMD FCTL FDATA FPTR Memory Management Registers Comment Command to execute Access mode and file number Data transfer and additional parameters File pointer (phrase selector) Busy and Error indication 16 16 16 16 (11) Register # of Bits STATUS 16 The status register contains two flags (table 25) to indicate if currently a file command is under execution and if the last file command terminated without error. A new command must not be written to FCMD while the last one is still running (STATUS:BSY=1). The only command that can be aborted is Compress File. Table 25 Memory Management Status Name BSY ERR Comment File command or decoder/encoder still running File command completed/aborted with error Register # of Bits STATUS 1 STATUS 1 Semiconductor Group 46 11.97 PSB 2168 Functional Description Writing to FCMD also resets the error bit in the status register. Table 26 shows the parameters defining the access mode and the access location. All parameters can only be written when no file command is currently running. They become effective after the completion of an open command. If another unit (e.g. speech coder) accesses the file, the file pointer is updated automatically. Therefore the controller can monitor the progress of recording or playing by reading the file pointer. Table 26 FCTL FCTL FCTL FCTL FPTR Memory Management Parameters Name MS MD TS FNO Comment Memory space (R/W or voice prompt) Access mode (audio or binary) Write timestamp (file open only) File number (active file) File pointer or phrase selector 1 1 1 8 16 Register # of Bits Commands are written to the FCMD register. The busy bit in the STATUS register is set within 125s. The command may start execution after a delay, however (see section 2.2.5). Some commands require additional parameters which are written prior to the command into the specified registers. Data transfer is done by the register FDATA (both reading and writing). 2.2.2 User Data Word The user data word consists of 12 bits that can be read or written by the user, two bits (R) that are reserved for future use and two read-only bits (D,M) which indicate the status of a file. 15 D M R R User Definable 0 If D is set, the file is marked for deletion and should not be used any more. This bit is maintained by the PSB 2168 for housekeeping. Semiconductor Group 47 11.97 PSB 2168 Functional Description 2.2.3 High Level Memory Management Commands This section describes each of the high level memory management commands in detail. These commands are sufficient for normal operation of an answering machine. In addition, there are four low level commands (section 2.2.4). These commands are only required for special tasks like in-system reprogramming of the voice prompt area. Memory Management - Commands 2.2.3.1 Initialize This command creates a directory, sets the external memory configuration and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory space is scanned for a valid directory. The PSB 2168 can either create an empty directory from scratch or leave the first n files of an existing directory untouched while deleting the remaining files (ARAM/DRAM only). This option is useful if due to an unexpected event (e.g. power loss during recording) some data is corrupted. In that case vital system information can still be recovered if it has been stored in the first files. Table 27 FCMD FCMD FCTL Initialize Memory Parameters Name CMD IN FNO Comment Initialize command code Confirmation for Initialization 0: delete no file 1: delete all files n: delete starting with file n Type of R/W memory (DRAM, Flash) Quality of R/W memory (Audio, Normal) Scan for voice prompt directory 5 1 8 Register # of Bits CCTL CCTL CCTL 2 1 1 MT MQ MV Table 28 FDATA Initialize Memory Results Name Comment Number of usable 1kByte blocks in R/W memory 16 Register # of Bits Possible Errors: * no R/W memory found * more than 59 bad blocks (flash and ARAM) * voice prompt directory requested, but not detected Note: This command must be given only once for flash devices. Semiconductor Group 48 11.97 PSB 2168 Functional Description 2.2.3.2 Activate This command activates an existing directory, sets the external memory configuration and delivers the size of usable memory in 1 kByte blocks. Furthermore the voice prompt memory space is scanned for a valid directory. Upon activation the PSB 2168 checks (in case of ARAM/DRAM only) the consistency of the directory in R/W memory space. It returns the first file that contains corrupted data (if any). If corrupted data is detected an initialization should be performed with the same file number as an input parameter. Table 29 FCMD CCTL CCTL CCTL Activate Memory Parameters Name CMD MT MQ MV Comment Activate command code Type of R/W memory (DRAM, Flash) Quality of R/W memory (Audio, Normal) Voice prompt directory available 5 2 1 1 Register # of Bits Table 30 FDATA FCTL Activate Memory Results Name FNO Comment Number of usable 1 kByte blocks in R/W memory n: number of first corrupted file 16 8 Register # of Bits Possible error conditions: * * * * * no memory connected no directory found device ID wrong (flash only) corrupted files found (see FCTL:FNO) directory corrupted This command can have three types of result as shown in table 31. Table 31 Result no error soft error Activate Memory Result Interpretation STATUS: FCTL: ERR FNO 0 1 0 n 1 Comment Command successful, memory activated. The first n-1 files are O.K. The memory is activated. The memory is not activated due to a hard error. hard error 1 Semiconductor Group 49 11.97 PSB 2168 Functional Description 2.2.3.3 Open File A specific file is opened for subsequent accesses with the specified access mode. Opening a new file automatically closes the currently open file and clears the file pointer. Opening file number 0 can be used to close all physical files. If the TS flag is set, the current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. Table 32 FCMD FCTL FCTL FCTL FCTL Open File Parameters Name CMD MS MD TS FNO Comment Open command code Memory space (R/W, voice prompt) Access mode (audio or binary) Write timestamp File number Register # of Bits Possible error conditions: * * * * * selected file marked for deletion, but not yet deleted by garbage collection memory space invalid new file selected, but memory full Note: In case of flash memory existing ones in the entries RTC1/RTC2 of the file descriptor cannot be altered. Therefore TS should be set only once during the lifetime of a file. 2.2.3.4 Open Next Free File The next free file is opened for subsequent write accesses with the specified access mode. The search starts at the specified file number. If the TS flag is set, the current content of RTC1 and RTC2 is written to the appropriate fields of the file descriptor in order to provide a timestamp. If a free file has been found, the file is opened and the file number is returned in FCTL:FNO. Otherwise an error is reported. Table 33 FCMD FCTL Open Next Free File Parameters Name CMD MD Comment Open Next Free File command code Access mode (audio or binary) 5 1 Register # of Bits Semiconductor Group 50 11.97 PSB 2168 Functional Description Table 33 FCTL FCTL : Open Next Free File Parameters Name TS FNO Comment Write timestamp Starting point (>0) 1 8 Register # of Bits Table 34 FCTL Open Next Free File Results Name FNO Comment File number 8 Register # of Bits Possible error conditions: * no unused file found * memory full Note: In case of flash memory existing ones cannot be altered. Therefore TS should be set only once during the lifetime of a file. Note: R/W-memory must be selected (FCTL:MS). Otherwise the result is unpredictable. 2.2.3.5 Seek The file pointer of the currently opened file is set to the specified position. If the current file is the phrase file the PSB 2168 starts the speech decoder immediately after the seek is finished. This is done by simply enabling the decoder. All other settings of the decoder remain unaffected. The BSY bit is first set during the file command. It is then reset for a short period until the speech decoder is enabled internally. It is then set again while the decoder is running and finally reset when the phrase is finished. Table 35 FCMD FPTR Seek Parameters Name CMD Comment Seek command code File pointer (phrase selector) 5 16 (11) Register # of Bits Possible error conditions: * file pointer out of range * phrase number out of range Semiconductor Group 51 11.97 PSB 2168 Functional Description 2.2.3.6 Cut File All units starting with the unit addressed by the file pointer are removed from the file. If all units are deleted the file is marked for deletion (see user data word). However, the associated file descriptor and memory space are released only after a subsequent garbage collection. Table 36 FCMD FPTR Cut File Parameters Name CMD Comment Cut command code Position of first unit to delete 5 16 Register # of Bits Possible error conditions: * file pointer out of range * voice prompt memory selected 2.2.3.7 Compress File An audio file that has been recorded in HQ mode can be recoded using LP mode. This reduces the file size to approximately one third of the original size. The speech quality, however, is somewhat lower compared to a signal that has been recorded in LP mode in the first place. This command can be aborted at any time and resumed later without loss of information. Prior to this command all files must be closed. Table 37 shows the parameters for this command. . Table 37 FCMD FCTL Compress File Parameters Name CMD FNO Comment Compress command code File number Register # of Bits Possible error conditions: * Semiconductor Group 52 11.97 PSB 2168 Functional Description 2.2.3.8 Memory Status This command returns the number of available 1 kB blocks in R/W memory space. Table 38 FCMD Memory Status Parameters Name CMD Comment Memory status code 5 Register # of Bits Table 39 FDATA Memory Status Results Name FREE Comment Number of free blocks 16 Register # of Bits Possible error conditions: * file open 2.2.3.9 Garbage Collection This command initiates a garbage collection. Until a garbage collection files that are marked for deletion still occupy the associated file descriptor and memory space. After the garbage collection these file descriptors and the associated memory space are available again. This command can optionally remap the directory. In this mode the remaining file descriptors are remapped to form a contiguous block starting with file number 1. The original order is preserved. This command requires that all files are closed, i.e. file 0 is opened. Independently of the selected directory only the read/write directory is used. Table 40 FCMD FCMD Garbage Collection Parameters Name CMD RD Comment Garbage Collection Command Code Remap Directory 5 1 Register # of Bits Possible error conditions: * file open 2.2.3.10 Access File Descriptor By this command the length, user data word and RTC1/RTC2 of a file descriptor can be read. The user data word can also be written. The file or the other entries of the file descriptor are not affected by this command. Semiconductor Group 53 11.97 PSB 2168 Functional Description Table 41 FCMD FDATA Access File Descriptor Parameters Name CMD Comment Read Access or Write Access command code User data (write access only) 5 16 Register # of Bits Table 42 FDATA Access File Descriptor Results Name Comment Content of selected entry (read access only) 16 Register # of Bits Possible error conditions: * none Note: In case of flash memory bits already set to 1 cannot be altered. Note: Do not use this command with the phrase file (fno = 255). 2.2.3.11 Read Data This command can be used in binary access mode only. A single word is read at the position given by the file pointer. The file pointer can be set by the Seek command. The file pointer is advanced by one word automatically. Table 43 FCMD Read Data Parameters Name CMD Comment Read Data Command Code 5 Register # of Bits Table 44 FDATA Read Data Results Name Comment Data word 16 Register # of Bits Possible error conditions: * file pointer out of range * phrase file selected * audio file selected Semiconductor Group 54 11.97 PSB 2168 Functional Description 2.2.3.12 Write Data This commands can be used in binary access mode only. A single word is written at the position of the file pointer. The file pointer is advanced by one word automatically. Note, that for FLASH memory only zeroes can be overwritten by ones. This restriction occurs only if an already used value within an existing file is to be overwritten. Table 45 FCMD FDATA Write Data Parameters Name CMD Comment Access Mode Command Code (including mode) Data word 5 16 Register # of Bits Possible error conditions: * * * * file pointer out of range (for existing files only) voice prompt memory selected memory full audio file selected Semiconductor Group 55 11.97 PSB 2168 Functional Description 2.2.4 Low Level Memory Management Commands These commands allow the direct access of any location (single word) of the external memory. Additionally it is possible to erase any block in case of a flash device. These commands should not be used during normal operation as they may interfere with the file system. No file must be open when one of these commands is given. The primary use of these commands is the in-system programming of a flash device with voice prompts. Please refer to the appropriate Application Notes. 2.2.4.1 Set Address This command sets the 24 bit address pointer APTR. Only the address bits A8-A23 are set, the address bits A0-A7 are automatically cleared. Table 46 FCMD FDATA Set Address Parameters Name CMD ADR Comment Set Address command code Address bits A8-A23 of address pointer APTR 5 16 Register # of Bits Possible error conditions: * file open 2.2.4.2 DMA Read This command reads a single word addressed by APTR. After the read access APTR is automatically incremented by one. Table 47 shows the parameters for this command. Table 47 FCMD DMA Read Parameters Name CMD Comment DMA Read command code 5 Register # of Bits Table 48 FDATA DMA Read Results Name DATA Comment Data read from address APTR. 16 Register # of Bits Possible error conditions: * file open Semiconductor Group 56 11.97 PSB 2168 Functional Description 2.2.4.3 DMA Write This command writes a single word to the location addressed by APTR. After the write access APTR is automatically incremented by one. Table 49 shows the parameters for this command. Table 49 FCMD FDATA DMA Write Parameters Name CMD DATA Comment DMA Write command code Data to be written to APTR 5 16 Register # of Bits Possible error conditions: * file open Note: If flash memory is connected the actual write is only performed when the last word within a page is written. Until then the data is merely buffered in the flash device. Please check the flash memory data sheets on page size. 2.2.4.4 Block Erase This command erases the physical block which includes the address given by APTR. The actual amount of memory erased by this command depends on the block size of the flash device. Table 50 shows the parameters for this command. Table 50 FCMD Block Erase Parameters Name CMD Comment Block Erase command code 5 Register # of Bits Possible error conditions: * file open * ARAM/DRAM configured Semiconductor Group 57 11.97 PSB 2168 Functional Description 2.2.5 Execution Time The execution time of the file commands is determined by four factors: 1. Internal state of the PSB 2168 2. Memory configuration 3. Memory state 4. Individual characteristics of the memory devices Therefore there is no general formula for an exact calculation of the execution time for file commands. For ARAM/DRAM items three and four are not significant as the memory access timing is always fixed and no additional delay is incurred for erasing memory blocks. However, the amount of memory has significant impact on the initialization in case of ARAM and flash. For flash devices the particular location of a write access in combination with the internal organization of the memory device may result in a block erase and subsequent write accesses in order to copy data. In this case the individual erase and write timing of the attached devices also prolongs the execution time. The first factor, the internal state of the PSB 2168, can influence all file commands regardless of the memory type attached. In general the PSB 2168 may delay any file command by up to 30 ms. However, it is possible to skip this delay if the following conditions hold: 1. The command is not initialize/activate 2. Neither the DTMF detector nor the speech coder nor the speech decoder are running If neither condition is violated then the PSB 2168 can be forced to start command execution immediately. This is done by setting the EIE bit in the FCMD register along with the command code. Table 51 gives an indication of the execution time for two typical memory configurations. Table 51 Command Initialize Activate Open File /Open Next Free File Seek (within 4 MBit File) Seek (within phrase file) Cut File Compress File Access File Descriptor Semiconductor Group 58 Execution Times ARAM (4 MBit) KM29LV040 40 s1) < 10 ms <10 ms <0.5 s <1 ms <5 ms #units * 30 ms <10 ms <11 s 3s <26 ms <0.5 s <1 ms <5 ms #units * 30 ms <10 ms 11.97 PSB 2168 Functional Description Table 51 Command Memory Status Read/Write Data Garbage Collection 1) Execution Times ARAM (4 MBit) KM29LV040 <10 ms <10 ms <20 ms <10 ms <10 ms 3s less than 20 ms for DRAM 2.2.6 Special Notes on File Commands 1. No MMU commands must be inserted between opening a file and writing data to it, either by writing data to a binary file or by enabling the coder for audio files. Therefore reading or writing the file descriptor (e.g. user data word) is only allowed after all data writing has happened. 2. If an audio file has been opened for replay, a Write File Descriptor Command must be followed by a Seek command before the decoder can be enabled. Semiconductor Group 59 11.97 PSB 2168 Functional Description 2.3 Miscellaneous Miscellaneous Miscellaneous Real Time Clock 2.3.1 The PSB 2168 supplies a real time clock which maintains time with a resolution of a second and a range of up to a year. There are two registers which contain the current time and date (table 52). Table 52 RTC1 RTC1 RTC2 RTC2 Real Time Clock Registers Name SEC MIN HR DAY Comment Seconds elapsed Minutes elapsed Hours elapsed Days elapsed 6 6 5 11 Register # of Bits The real time clock maintains time during normal mode and power down mode only if the auxiliary oscillator OSC is running and the RTC is enabled. Note: Writing out-of-range values to RTC1 and RTC2 results in undefined operation of the RTC 2.3.2 SPS Control Register The two SPS outputs (SPS0, SPS1) can be used as either general purpose outputs, extended address outputs for Voice Prompt EPROM or as status register outputs. Table 53 shows the associated register. Table 53 SPSCTL SPSCTL SPSCTL SPSCTL SPS Registers 1 1 3 4 SP0 SP1 MODE POS Output Value of SPS0 Output Value of SPS1 Mode of Operation Position for status register window When used as status register outputs, the status register bit at position POS appears at SPS0 and the bit at position POS+1 appears at SPS1. This mode of operation can be used for debugging purposes or direct polling of status register bits. 2.3.3 Reset and Power Down Mode The PSB 2168 can be in either reset mode, power down mode or active mode. During reset the PSB 2168 clears the hardware configuration registers and stops both internal Semiconductor Group 60 11.97 PSB 2168 Functional Description and external activity. The address lines MA0-MA15 provide a weak low until they are actually used as address lines (strong outputs) or auxiliary port pins (I/O). In reset mode the hardware configuration registers can be read and written. With the first access to a read/write register the PSB 2168 enters active mode. In this mode the main oscillator is running and normal operation takes place. By setting the power down bit (PD) the PSB 2168 can be brought to power down mode. Table 54 CCTL Power Down Bit Name PD Comment power down mode 1 Register # of Bits In power down mode the main oscillator is stopped and, depending on HWCONFIG2:PPM), the memory control lines are released (weak high). Depending on the configuration (ARAM/DRAM, APP) the PSB 2168 may still generate external activity (e.g. refresh cycles). The PSB 2168 enters active mode again upon an access to a read/ write register. Figure 29 shows a state chart of the modes of the PSB 2168. Reset Mode R/W reg. access RST=1 RST=1 CCTL.PD=1 Active Mode R/W reg. access Power Down Mode Figure 29 Operation Modes - State Chart 2.3.4 Interrupt The PSB 2168 can generate an interrupt to inform the host of an update of the STATUS register according to table 55. An interrupt mask register (INTM) can be used to disable or enable the interrupting capability of each bit of the STATUS register except ABT individually. Semiconductor Group 61 11.97 PSB 2168 Functional Description Table 55 STATUS (old) RDY=0 CIA=0 CD=0 CD=1 CPT=0 CPT=1 CNG=0 DTV=0 DTV=1 ATV=0 ATV=1 BSY=1 SD=0 SD=1 Interrupt Source Summary STATUS Set by (new) RDY=1 CIA=1 CD=1 CD=0 CPT=1 CPT=0 CNG=1 DTV=1 DTV=0 ATV=1 ATV=0 BSY=0 SD=1 SD=0 Command completed New Caller ID byte available Carrier detected Carrier lost Call progress tone detected Call progress tone lost Fax calling tone detected DTMF tone detected DTMF tone lost Alert tone detected Alert tone lost File command completed Speech activity detected Speech activity lost Reset by Command issued CIDCTL0 read Carrier lost Carrier detected CPT lost CPT detected CNG lost DTMF tone lost DTMF tone detected Alert tone lost Alert tone detected New command issued Speech activity lost Speech activity detected An interrupt is internally generated if any combination of these events occurs and the interrupt is not masked. The interrupt is cleared when the host reads the STATUS register. If a new event occurs while the host reads the status register, the status register is updated after the current access is terminated and a new interrupt is generated immediately after the access has ended. Note: If the internal interrupt occurs after the controller has already selected the device but not yet read the STATUS word, then the STATUS word is updated and the internal interrupt is cleared. Therefore the controller should always evaluate the STATUS word when read. 2.3.5 Abort If the PSB 2168 cannot continue the current operations in progress (e.g. due to a transient loss of power) it stops operation and initializes all read/write registers to their reset state. After that it sets the ABT bit of the STATUS register and generates an interrupt. The PSB 2168 discards all commands with the exception of a write command to the revision register while ABT is set. Only after the write command to the revision register (with any value) the ABT bit is reset and a reinitialization can take place. Semiconductor Group 62 11.97 PSB 2168 Functional Description 2.3.6 Revision Register The PSB 2168 contains a revision register. This register is read only and does not influence operation in any way. A write to the revision register clears the ABT bit of the STATUS register but does not alter the content of the revision register. 2.3.7 Hardware Configuration The PSB 2168 can be adapted to various external hardware configurations by four special registers: HWCONFIG0 to HWCONFIG3. These registers are usually only written once during initialization and must not be changed while the PSB 2168 is in active mode. It is mandatory that the programmed configuration reflects the external hardware for proper operation. Special care must be taken to avoid I/O conflicts or excess current by enabling inputs without an external driving source. Table 56 can be used as a checklist. Table 56 Register HWCONFIG0 HWCONFIG0 Hardware Configuration Checklist Name OSC Value 1 Check FRDY must not float OSC1/2 must be connected to a crystal PFRDY 1 Semiconductor Group 63 11.97 PSB 2168 Functional Description 2.3.8 Auxiliary Clock Generation The PSB 2168 can generate a data clock (at AFECLK) and a frame synchronization signal (at AFEFS) for typical single channel codecs. The PSB 2168 provides two pairs of frequencies according to table 57. Table 57 CM1 0 0 1 1 0 1 0 1 Auxiliary Clock Generation CM0 AFECLK L undefined 512 kHz AFEFS L undefined 8 kHz Comment auxiliary clock generation disabled reserved e.g. MC145480 e.g. TP3054 1.536 MHz 8 kHz Note: These frequencies are derived from the main oscillator. Therefore the values listed in the table are only valid for the specified oscillator frequencies (see HWCONFIG1) 2.3.9 Dependencies of Modules There are some restrictions concerning the modules that can be enabled at the same time (table 58). A checked cell indicates that the two modules (defined by the row and the column of the cell) must not be enabled at the same time. Table 58 Dependencies of Modules Speech Encoder Speech Encoder Speech Decoder Line EC (24 ms) DTMF Detector File Command 1) Speech Decoder X Line EC DTMF File (24 ms) Detector Command X X1) B,O,I B,O,I B,O B,I B,O B,I X X B,O,I X1) B,O,I if Speech Decoder is running at slow speed There are three classes of file commands denoted by the letters B, O and I. Table 59 shows the definition of these classes: Semiconductor Group 64 11.97 PSB 2168 Functional Description Table 59 B O I File Command Classes Class Description Background commands (Activate, Recompress, Garbage Collection, Initialize) Open Commands (Open, Open Next Free File) Any command executed with EIE=1 (i.e. immediate execution) Examples: * The line echo canceller (in 24 ms mode) cannot be enabled when the speech decoder is running at slow speed. * If the DTMF detector is running, none of the background file commands (B) must be executed. In addition, no file command must be executed with immediate execution enabled (I). However, files my be opened and other commands (like read or write) may be executed without immediate execution enabled. Semiconductor Group 65 11.97 PSB 2168 Functional Description 2.4 Interfaces Interfaces Interfaces This section describes the interfaces of the PSB 2168. The PSB 2168 supports both an IOM(R)-2 interface with single and double clock mode and a strobed serial data interface (SSDI). However, these two interfaces cannot be used simultaneously as they share some pins. Both interfaces are for data transfer only and cannot be used for programming the PSB 2168. Table 60 lists the features of the two alternative interfaces. Table 60 Signals Channels (bidirectional) Code SSDI vs. IOM(R)-2 Interface IOM(R)-2 4 2 linear PCM, A-law, -law 6 1 linear PCM by signal (DXST, DRST) SSDI Synchronization within frame by timeslot (programmable) 2.4.1 IOM(R)-2 Interface The data stream is partitioned into packets called frames. Each frame is divided into a fixed number of timeslots. Each timeslot is used to transfer 8 bits. Figure 30 shows a commonly used terminal mode (three channels ch0, ch1 and ch2 with four timeslots each). The first timeslot (in figure 30: B1) is denoted by number 0, the second one (B2) by 1 and so on. 125 s FSC DD/DU B1 B2 ch0 M0 CI0 IC1 IC2 ch1 M1 CI1 ch2 Figure 30 IOM(R)-2 Interface - Frame Structure The signal FSC is used to indicate the start of a frame. Figure 31 shows as an example two valid FSC-signals (FSC, FSC*) which both indicate the same clock cycle as the first clock cycle of a new frame (T1). Note: Any timeslot (including M0, CI0, ...) can be used for data transfer. However, programming is not supported via the monitor channels. Semiconductor Group 66 11.97 PSB 2168 Functional Description T1 DCL T2 FSC FSC* Figure 31 IOM(R)-2 Interface - Frame Start The PSB 2168 supports both single clock mode and double clock mode. In single clock mode, the bit rate is equal to the clock rate. Bits are shifted out with the rising edge of DCL and sampled at the falling edge. In double clock mode, the clock runs at twice the bit rate. Therefore for each bit there are two clock cycles. Bits are shifted out with the rising edge of the first clock cycle and sampled with the falling edge of the second clock cycle. Figure 32 shows the timing for single clock mode and figure 33 shows the timing for double clock mode. T1 DCL T2 DU/DX bit 0 bit 1 bit 2 DD/DR bit 0 bit 1 bit 2 Figure 32 IOM(R)-2 Interface - Single Clock Mode Semiconductor Group 67 11.97 PSB 2168 Functional Description T1 DCL T2 T3 T4 T5 DU/DX bit 0 bit 1 bit 2 DD/DR bit 0 bit 1 Figure 33 IOM(R)-2 Interface - Double Clock Mode The PSB 2168 supports up to two channels simultaneously for data transfer. Both the coding (PCM or linear) and the data direction (DD/DU assignment for transmit/receive) can be programmed individually for each channel. Table 61 shows the registers used for configuration of the IOM(R)-2 interface. Table 61 IOM(R)-2 Interface Registers Name EN DCL NTS EN TS DD PCM PCD EN TS DD PCM PCD Comment Interface enable Selection of clock mode Number of timeslots within frame Channel 1 enable First timeslot (channel 1) Data Direction (channel 1) 8 bit code or 16 bit linear PCM (channel 1) 8 bit code (A-law or -law, channel 1) Channel 2 enable First timeslot (channel 2) Data Direction (channel 2) 8 bit code or 16 bit linear PCM (channel 2) 8 bit code (A-law or -law, channel 2) Register # of Bits SDCONF 1 SDCONF 1 SDCONF 6 SDCHN1 1 SDCHN1 6 SDCHN1 1 SDCHN1 1 SDCHN1 1 SDCHN2 1 SDCHN2 6 SDCHN2 1 SDCHN2 1 SDCHN2 1 In A-law or -law mode, only 8 bits are transferred and therefore only one timeslot is needed for a channel. In linear mode, 16 bits are needed for a single channel. In this mode, two consecutive timeslots are used for data transfer. Bits 8 to 15 are transferred Semiconductor Group 68 11.97 PSB 2168 Functional Description within the first timeslot and bits 0 to 7 are transferred within the next timeslot. The first timeslot must have an even number. The most significant bit is always transmitted first. Semiconductor Group 69 11.97 PSB 2168 Functional Description 2.4.2 SSDI Interface The SSDI interface is intended for seamless connection to low-cost burst mode controllers (e.g. PMB 27251) and supports a single channel in each direction. The data stream is partitioned into frames. Within each frame one 16 bit value can be sent and received by the PSB 2168. The start of a frame is indicated by the rising edge of FSC. Data is always sampled at the falling edge of DCL and shifted out with the rising edge of DCL. The SSDI transmitter and receiver are operating independently of each other except that both use the same FSC and DCL signal. 2.4.2.1 SSDI Interface - Transmitter The PSB 2168 indicates outgoing data (on signal DX) by activating DXST for 16 clocks. The signal DXST is activated with the same rising edge of DCL that is used to send the first bit (Bit 15) of the data. DXST is deactivated with the first rising edge of DCL after the last bit has been transferred. The PSB 2168 drives the signal DX only when DXST is activated. Figure 34 shows the timing for the transmitter. 125 s FSC DXST DCL DU/DX bit 15 bit 14 bit 1 bit 0 Figure 34 SSDI Interface - Transmitter Timing 2.4.2.2 SSDI Interface - Receiver Valid data is indicated by an active DRST pulse. Each DRST pulse must last for exactly 16 DCL clocks. As there may be more than one DRST pulses within a single frame the PSB 2168 can be programmed to listen to the n-th pulse with n ranging from 1 to 16. In order to detect the first pulse properly, DRST must not be active at the rising edge of FSC. In figure 35 the PSB 2168 is listening to the third DRST pulse (n=3). Semiconductor Group 70 11.97 PSB 2168 Functional Description FSC DRST active pulse (n=3) Figure 35 SSDI Interface - Active Pulse Selection Figure 36 shows the timing for the SSDI receiver. 125 s FSC DRST DCL DD/DR bit 15 bit 14 bit 1 bit 0 Figure 36 SSDI Interface - Receiver Timing Table 62 shows the registers used for configuration of the SSDI interface. Table 62 SSDI Interface Register Name NAS Comment Number of active DRST strobe Register # of Bits SDCHN1 4 Semiconductor Group 71 11.97 PSB 2168 Functional Description 2.4.3 Serial Control Interface The serial control interface (SCI) uses four lines: SDR, SDX, SCLK and CS. Data is transferred by the lines SDR and SDX at the rate given by SCLK. The falling edge of CS indicates the beginning of an access. Data is sampled by the PSB 2168 at the rising edge of SCLK and shifted out at the falling edge of SCLK. Each access must be terminated by a rising edge of CS. The accesses to the PSB 2168 can be divided into three classes: 1. Configuration Read/Write 2. Status/Data Read 3. Register Read/Write If the PSB 2168 is in power down mode, a read access to the status register does not deliver valid data with the exception of the RDY bit. After the status has been read the access can be either terminated or extended to read data from the PSB 2168. A register read/write access can only be performed when the PSB 2168 is ready. The RDY bit in the status register provides this information. Any access to the PSB 2168 starts with the transfer of 16 bits to the PSB 2168 over line SDR. This first word specifies the access class, access type (read or write) and, if necessary, the register accessed. If a configuration register is written, the first word also includes the data and the access is terminated. Likewise, if a register read is issued, the access is terminated after the first word. All other accesses continue by the transfer of the status register from the PSB 2168 over line SDX. If a register (excluding configuration) is to be written, the next 16 bits containing the data are transferred over line SDR and the access is terminated. Figures 37 to 40 show the timing diagrams for the different access classes and types to the PSB 2168. CS SCLK SDR c15 c14 c1 c0 SDX s15 s14 s1 s0 INT c15,..,c0: command word for status register read : s15,..,s0: status register: Figure 37 Status Register Read Access Semiconductor Group 72 11.97 PSB 2168 Functional Description CS SCLK SDR c15 c14 c1 c0 SDX s15 s14 s1 s0 d15 d14 d1 d0 c15,..,c0: command word for data read: s15,..,s0: status register: d15,..,d0: data to be read: Figure 38 Data Read Access CS SCLK SDR c15 c14 c1 c0 d15 d14 d1 d0 SDX s15 s14 s1 s0 c15,..,c0: command word for register write: s15,..,s0: status register: d15,..,d0: data to be written : Figure 39 Register Write Access Semiconductor Group 73 11.97 PSB 2168 Functional Description CS SCLK SDR c15 c14 c1 c0 SDX s15 s14 s1 s0 d15 d14 d1 d0 c15,..,c0: command word for configuration register read: s15,..,s0: status register : d15,..,d0: data to be read: Figure 40 Configuration Register Read Access Configuration registers at even adresses use bit positions d 7-d0 while configuration registers at odd adresses use bit positions d15-d8. CS SCLK SDR c15 c14 c1 c0 c15,..,c0: command word for configuration register write: or register read: Figure 41 Configuration Register Write Access or Register Read Command The internal interrupt signal is cleared when the first bit of the status register is put on SDX. However, externally the signal INT is deactivated as long as CS stays low. If the internal interrupt signal is not cleared or another event causing an interrupt occurs while the microcontroller is already reading the status belonging to the first event then INT goes low again immediately after CS is removed. The timing is shown in figure 37. Table 63 shows the formats of the different command words. All other command words are reserved. Semiconductor Group 74 11.97 PSB 2168 Functional Description Table 63 Command Words for Register Access 15 Read Status Register or Data Read Access Read Register Write Register Read Configuration Reg. Write Configuration Reg. 0 0 0 0 0 14 0 1 1 1 1 13 1 0 0 1 1 12 1 1 0 1 0 0 0 0 0 R W 0 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 REG REG 0 0 0 0 0 0 0 DATA In case of a configuration register write, W determines which configuration register is to be written (table 64): Table 64 9 0 0 1 1 8 0 1 0 1 Address Field W for Configuration Register Write Register HWCONFIG 0 HWCONFIG 1 HWCONFIG 2 HWCONFIG 3 In case of a configuration register read, R determines which pair of configuration registers is to be read (table 65): Table 65 9 0 1 Address Field R for Configuration Register Read Register pair HWCONFIG 0 / HWCONFIG 1 HWCONFIG 2 / HWCONFIG 3 Note: Reading any register except the status register or a hardware configuration register requires at least two accesses. The first access is a register read command (figure 41). With this access the register address is transferred to the. After that access data read accesses (figure 38) must be executed. The first data read access with STATUS:RDY=1 delivers the value of the register. Semiconductor Group 75 11.97 PSB 2168 Functional Description 2.4.4 Memory Interface The PSB 2168 supports either Flash Memory or ARAM/DRAM as external memory for storing messages. If ARAM/DRAM is used, an EPROM can be added optionally to support read-only messages (e.g. voice prompts). Table 66 summarizes the different configurations supported. Table 66 Mbit 1 2 4 4 8 16 16 32 32 64 64 128 4-128 16-128 Supported Memory Configurations Type ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM ARAM/DRAM FLASH FLASH 16Mx4 16Mx4 8Mx8 16Mx4 512kx8 devices 2Mx8 devices 4Mx4 2x2Mx8 1Mx4 4Mx4 2Mx8 4Mx4 Bank 0 (D0-D3) 256kx4 256kx4 1Mx4 512kx8 1Mx4 2k or 4k refresh 2k refresh 2k or 4k refresh 2k refresh 4k or 8k refresh 4k or 8k refresh 4k or 8k refresh KM29N040 KM29N16000 Bank 1 (D4-D7) 256kx4 Comment If ARAM/DRAM is used, the total amount of memory must be a power of two and all devices must be of the same type. The pin FRDY must be tied high. For flash devices, the PSB 2168 supports in-circuit programming of voice prompts by releasing the control lines during reset and (optionally) power down. Instead of actively driving the lines FCS, FOE, FWE, FCLE and ALE these lines are pulled high by a weak pullup during reset and (optionally) power down. Semiconductor Group 76 11.97 PSB 2168 Functional Description 2.4.4.1 ARAM/DRAM Interface The PSB 2168 supports up to two banks of memory which may be 4 bit or 8 bit wide (Figure 42). If both banks are used they must be populated identically. MA0-MA15 MD0-MD3 RAS CAS0 W A0-A12 D0-D3 RAS CAS W OE MA0-MA15 MD0-MD7 RAS CAS0 W A0-A12 D0-D7 RAS CAS W OE PSB 2168 PSB 2168 single 4 bit bank single 8 bit bank MA0-MA15 MD0-MD3 RAS CAS0 W A0-A12 D0-D3 RAS CAS W OE MA0-MA15 MD0-MD7 RAS CAS0 W A0-A12 D0-D7 RAS CAS W OE PSB 2168 PSB 2168 A0-A12 MD4-MD7 D0-D3 RAS CAS1 CAS W OE CAS1 A0-A12 D0-D7 RAS CAS W OE two 4 bit banks two 8 bit banks Figure 42 ARAM/DRAM Interface - Connection Diagram Semiconductor Group 77 11.97 PSB 2168 Functional Description The PSB 2168 also supports different internal organizations of ARAM/DRAM chips. Table 67 shows the necessary connections on the address bus. Table 67 256k x4 512k x8 1M x4 4M x4 (2k refresh) 4M x4 (4k refresh) 2M x8 16M x4 (4k refresh) 16M x4 (8k refresh) 8M x8 (4k refresh) 8M x8 (8k refresh) 1) Address Line Usage (ARAM/DRAM Mode) CS91) MA0-MA8 MA9 1 1 0 0 0 0 0 0 0 0 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A0-A8 A9 A9 A9 A9 A9 A9 A9 A9 A9 A10 A10 A10 A10 A10 A10 A10 A11 A11 A11 A11 A12 A12 A11 MA10 MA11 MA12 MA13 ARAM/DRAM see chip control register CCTL The timing of the ARAM/DRAM interface is shown in figures 43 to 45. The timing is derived form the internal memory clock MCLK* which runs at a quarter of the system clock. MCLK* MA0-MA13 RAS CAS0,CAS1 MD0-MD7 Figure 43 ARAM/DRAM Interface - Read Cycle Timing row addr. col. addr. Semiconductor Group 78 11.97 PSB 2168 Functional Description MCLK* MA0-MA13 RAS CAS0,CAS1 W MD0-MD7 data out row addr. col. addr. Figure 44 ARAM/DRAM Interface - Write Cycle Timing MCLK* RAS CAS0,CAS1 Figure 45 ARAM/DRAM Interface - Refresh Cycle Timing The PSB 2168 ensures that RAS remains inactive for at least one MCLK*-cycle between successive accesses. The frequency at which refresh cycles are performed is shown in table 68. Table 68 64 kHz 1) Refresh Frequency Selection Comment Memory access (e.g. recording) in progress Refresh frequency 8, 16, 32 or 64 kHz1) No memory access in progress or power-down as programmed by HWCONFIG2:RSEL Semiconductor Group 79 11.97 PSB 2168 Functional Description 2.4.4.2 EPROM Interface The PSB 2168 supports an EPROM in parallel with ARAM/DRAM. This interface is always 8 Bits wide and supports a maximum of 256 kB. Figure 46 shows a connection diagram and figure 47 the timing. This interface supports read cycles only. SPS1 SPS0 MA0-MA15 MD0-MD7 VPRD A17 A16 A0-A15 D0-D7 CE OE PSB 2168 Figure 46 EPROM Interface - Connection Diagram MCLK* MA0-MA15 VPRD MD0-MD7 Figure 47 EPROM Interface - Read Cycle Timing Note: In order to access more than 64 kB the pins SPS0 and SPS1 can be programmed to provide the address lines A16 and A17. In this mode A16 and A17 remain stable during the whole read cycle. See the register SPSCTL for programming information. Semiconductor Group 80 11.97 PSB 2168 Functional Description 2.4.4.3 Flash Memory Interface The PSB 2168 has special support for the KM29N040 and KM29N16000 or equivalent devices. No external components are required for up to four KM29N040. Figure 48 shows the connection diagram for a single device. MD0-MD7 ALE FCS FOE FWR FCLE FRDY D0-D7 ALE CE RE WE CLE R/B +5V WP PSB 2168 Figure 48 Flash Memory Interface - Connection Diagram Table 69 shows the signals output during a device access on the MA-lines. The address bits can used by an external decoder. Up to four KM29N040 are supported directly by the decoded select signals FCS0-FCS3. Table 69 MA11 FCS3 Address Line Usage (Samsung Mode) MA10 FCS2 MA9 FCS1 MA8 FCS0 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 A23 A22 A21 A20 A19 A18 A17 A16 Semiconductor Group 81 11.97 PSB 2168 Functional Description Figure 49 shows an application with three KM29N040 devices. WP D0-D7 CE RE WE R/B CLE ALE MD0-MD7 FOE FWR FRDY FCLE ALE MA8 MA9 MA10 D0-D7 CE RE WE R/B CLE ALE WP D0-D7 CE RE WE R/B CLE ALE PSB 2168 WP +5V Figure 49 Flash Memory Interface - Multiple Devices An access to the Flash Memory can consist of several partial access cycles where only the timing of the partial access cycles is defined but not the time between two adjacent partial access cycles. The PSB 2168 performs three types of partial access cycles: 1. Command write 2. Address write 3. Data read/write Table 70 shows the supported accesses and the corresponding partial access cycles. Table 70 Flash Memory Command Summary Command Address Address Address # of Data Command write write 1 write 2 write 3 read/write write FF 70 60 00 80 A8-A15 A0-A7 A0-A7 A16-A23 A8-A15 A8-A15 A16-A23 A16-A23 1 1-32 1-32 D0 10 Access RESET STATUS READ BLOCK ERASE READ WRITE Semiconductor Group 82 11.97 PSB 2168 Functional Description The timing for the partial access cycles is shown in figures 50 to 51. Note that both FCS and MA0-MA15 remain stable between the first and the last partial access of a device access. MCLK* MA0-MA11 FCS FWR FCLE MD0-MD7 data out Figure 50 Flash Memory Interface - Command Write t0 t1 t2 t3 MCLK* FWR ALE MD0-MD7 data out address latch cycle Figure 51 Flash Memory Interface - Address Write As there is no access that starts or stops with an address write cycle (figure 51) FCS is already low at the start of this cycle and also remains low. Semiconductor Group 83 11.97 PSB 2168 Functional Description t0 t1 t2 t3 MCLK* FWR MD0-MD7 data out write cycle Figure 52 Flash Memory Interface - Data Write As there is no access that starts or stops with a data write cycle (figure 52) FCS is already low at the start of this cycle and also remains low. t0 t1 t2 t3 MCLK* FOE MD0-MD7 data in read cycle Figure 53 Flash Memory Interface - Data Read If the device access ends with a read cycle, the FCS-signals go inactive after t3 of the last read cycle. The data is latched at the rising edge of FOE. Semiconductor Group 84 11.97 PSB 2168 Functional Description 2.4.5 Auxiliary Parallel Port The PSB 2168 provides an auxiliary parallel port if the memory interface is in Samsung mode and only one device is used. In this case the lines MA0 to MA15 are not needed for the memory interface and can therefore be used for an auxiliary parallel port. This port has two modes: static mode and multiplex mode. 2.4.5.1 Static Mode In static mode all pins of the auxiliary parallel port interface have identical functionality. Any pin can be configured as an output or an input. Pins configured as outputs provide a static signal as programmed by the controller. Pins configured as inputs are monitoring the signal continuously without latching. The controller always reads the current value. Table 71 shows the registers used for static mode. Table 71 DOUT3 DIN DDIR 2.4.5.2 Static Mode Registers 16 16 16 Output signals (for pins configured as outputs) Input signals (for pins configured as inputs) Pin direction Register # of bits Comment Multiplex Mode In multiplex mode, the PSB 2168 uses MA12-MA15 to distinguish four timeslots. Each timeslot has a duration of approximately 2 ms. The timeslots are separated by a gap of approximately 125 s in which none of the signals at MA12-MA15 are active. The PSB 2168 multiplexes three more output registers to MA0-MA11 in timeslots 0, 1 and 2. In timeslot 3 the direction of the pins can be programmed. For input pins, the signal is latched at the falling edge of MA15. Table 72 shows the registers used for multiplex mode. This mode is useful for scanning keys or controlling seven segment LED displays. Table 72 DOUT0 DOUT1 DOUT2 DOUT3 DIN DDIR Multiplex Mode Registers 12 12 12 12 12 12 Output signals on MA0-MA11 while MA15=1 Output signals on MA0-MA11 while MA14=1 Output signals on MA0-MA11 while MA13=1 Output signals (for pins configured as outputs) while MA12=1 Input signals (for pins configured as inputs) at falling edge of MA12 Pin direction during MA12=1 85 11.97 Register # of bits Comment Semiconductor Group PSB 2168 Functional Description Figure 54 shows the timing diagram for multiplex mode. 2 ms MA15 MA14 MA13 MA12 MA0-MA11 DOUT0 DOUT1 DOUT2 DIN/DOUT3 DOUT0 Figure 54 Auxiliary Parallel Port - Multiplex Mode Note: In either mode the voltage at any pin (MA0 to MA15) must not exceed VDD. Semiconductor Group 86 11.97 PSB 2168 Detailed Register Description 3 Detailed Register Description The PSB 2168 has a single status register (read only) and an array of data registers (read/write). The purpose of the status register is to inform the external microcontroller of important status changes of the PSB 2168 and to provide a handshake mechanism for data register reading or writing. If the PSB 2168 generates an interrupt, the status register contains the reason of the interrupt. 3.1 15 RDY 1) Status Register 0 ABT 0 0 CIA CD CPT CNG SD ERR BSY DTV ATV -1) -1) -1) undefined RDY Ready 0: The last command (if any) is still in progress. 1: The last command has been executed. ABT Abort 0: No exception during operation 1: Some exception other than reset caused the PSB 2168 to abort any operation currently in progress. The external microcontroller should reinitialize the PSB 2168 to ensure proper operation. The ABT bit is cleared by writing any value to register REV. No other command is accepted by the PSB 2168 while ABT is set. CIA Caller ID Available 0: No new data for caller ID 1: New caller ID byte available CD Carrier Detect 0: No carrier detected 1: Carrier detected Semiconductor Group 87 11.97 PSB 2168 Detailed Register Description CPT Call Progress Tone 0: Currently no call progress tone detected or pause detected (raw mode) 1: Currently a call progress is detected CNG Fax Calling Tone 0: Currently no fax calling tone detected 1: Currently a fax calling tone is detected SD Speech Detected 0: No speech detected 1: Speech signal at input of coder ERR Error (File Command) 0: No error 1: Last file command resulted in an error BSY Busy (File Command) 0: File system idle 1: File system still busy (also set during encoding/decoding) DTV DTMF Tone Valid 0: No new DTMF code available 1: New DTMF code available in DDCTL ATV Alert Tone Valid 0: No new alert tone code available 1: New alert tone code available in ADCTL0 Semiconductor Group 88 11.97 PSB 2168 Detailed Register Description 3.2 Hardware Configuration Registers HWCONFIG 0 - Hardware Configuration Register 0 7 PD 0 RTC OSC PPSDI PFRDY PPINT 0 PPSDX PPSDX Push/Pull for SDX 0: The SDX pin has open-drain characteristic 1: The SDX pin has push/pull characteristic PPINT Push/Pull for INT 0: The INT pin has open-drain characteristic 1: The INT pin has push/pull characteristic PFRDY Pullup for FRDY 0: The internal pullup resistor of pin FRDY is enabled 1: The internal pullup resistor of FRDY is disabled PPSDI Push/Pull for SDI interface 0: The DU and DD pins have open-drain characteristic 1: The DU and DD pins have push/pull characteristic OSC Enable Auxiliary Oscillator 0: The auxiliary oscillator (OSC1, OSC2) is disabled 1: The auxiliary oscillator (OSC1, OSC2) is enabled RTC Enable Real Time Clock 0: The real time clock is disabled 1: The real time clock (RTC) is enabled. PD Power Down (read only) 0: The PSB 2168 is in active mode 1: The PSB 2168 is in power down mode Semiconductor Group 89 11.97 PSB 2168 Detailed Register Description HWCONFIG 1 - Hardware Configuration Register 1 7 APP 0 0 1 XTAL 0 SSDI APP Auxiliary Parallel Port 7 0 0 1 1 6 0 1 0 1 Description normal (ARAM/DRAM, Intel type flash, voice prompt EPROM) APP static mode APP multiplex mode reserved XTAL XTAL Frequency 2 0 0 1 1 1) 1 0 1 0 1 Factor p1) reserved 4.5 4 reserved Description reserved 31.104 MHz 27.648 MHz reserved The factor p is needed to calculate the clock frequency at AFECLK. SSDI SSDI Interface Selection 0: IOM(R)-2 Interface 1: SSDI Interface Semiconductor Group 90 11.97 PSB 2168 Detailed Register Description HWCONFIG 2 - Hardware Configuration Register 2 7 PPM ESDX ESDR 0 0 RSEL 0 PPM Push/Pull for Memory Interface (reset, power down) 0: The signals for the memory interface have push/pull characteristic 1: The signals for the memory interface have pullup/pulldown characteristic ESDX Edge Select for DX 0: DX is transmitted with the rising edge of DCL 1: DX is transmitted with the falling edge of DCL ESDR Edge Select for DR 0: DR is latched with the falling edge of DCL 1: DR is latched with the rising edge of DCL RSEL Refresh Select 1 0 0 1 1 0 0 1 0 1 Description 64 kHz refresh frequency 32 kHz refresh frequency 16 kHz refresh frequency 8 kHz refresh frequency Semiconductor Group 91 11.97 PSB 2168 Detailed Register Description HWCONFIG 3 - Hardware Configuration Register 3 7 0 0 0 0 0 0 CM1 0 CM0 CM1 Clock Master 1 0: Clock generation at AFEFS and AFECLK disabled 1: Clock generation at AFEFS and AFECLK enabled CM0 Clock Master 0 0: 512 kHz (AFECLK) 1: 1.536 MHz (AFECLK) Semiconductor Group 92 11.97 PSB 2168 Detailed Register Description 3.3 Read/Write Registers The following sections contains all read/write registers of the PSB 2168. The register addresses are given as hexadecimal values. Registers marked with an R are affected by reset or a wake up after power down. All other registers retain their previous value. No access must be made to addresses other than those associated with a read/write register. Furthermore parameters of a functional unit must not be altered while the unit is enabled. Parameters that can be changed on the fly (taking effect while the functional unit is enabled) are marked individually. 3.3.1 00h 01h R 02h R 0Ah R 0Bh R 0ChR 0DhR 0Eh R 0Fh R 10h R 11h R 12h 13h 14h 15h 16h R 17h 18h 19h 1Ah R 1Bh 1ChR 1Dh 20h R 21h 22h 23h 24h 25h R Register Table Long Name Page REV CCTL INTM SDCONF SDCHN1 IFS3 SDCHN2 IFS4 IFG5 UA DGCTL DGF1 DGF2 DGL DGATT CNGCTL CNGBT CNGLEV CNGRES ATDCTL0 ATDCTL1 CIDCTL0 CIDCTL1 CPTCTL CPTTR CPTMN CPTMX CPTDT LECCTL Revision................................................................................ 96 Chip Control ......................................................................... 97 Interrupt Mask Register ........................................................ 98 Serial Data Interface Configuration ...................................... 99 Serial Data Interface Channel 1 ......................................... 100 Interface Select 3 ............................................................... 102 Serial Data Interface Channel 2 ......................................... 103 Interface Select 4 ............................................................... 104 Interface Gain 5.................................................................. 105 Universal Attenuator........................................................... 106 DTMF Generator Control.................................................... 107 DTMF Generator Frequency 1 ........................................... 108 DTMF Generator Frequency 2 ........................................... 109 DTMF Generator Level....................................................... 110 DTMF Generator Attenuation ............................................. 111 Calling Tone Control........................................................... 112 CNG Burst Time ................................................................. 113 CNG Minimal Signal Level ................................................. 114 CNG Signal Resolution ...................................................... 115 Alert Tone Detection 0........................................................ 116 Alert Tone Detection 1........................................................ 117 Caller ID Control 0.............................................................. 118 Caller ID Control 1.............................................................. 119 Call Progress Tone Control ................................................ 120 Call Progress Tone Thresholds.......................................... 121 CPT Minimum Times.......................................................... 122 CPT Maximum Times......................................................... 123 CPT Delta Times ................................................................ 124 Line Echo Cancellation Control .......................................... 125 Address. Name Semiconductor Group 93 11.97 PSB 2168 Detailed Register Description 26h 27h 28h 29h R 2Ah 2Bh 2Eh R 2Fh 30h R 31h 32h 34h R 38h R 39h R 3Ah 3Bh 3Ch 3Dh 3Eh 40h R 41h R 42h R 43h R 47h R 48h R 49h R 4Ah R 4Bh R 4ChR 4DhR 4Eh 4Fh R LECLEV LECATT LECMGN DDCTL DDTW DDLEV FCFCTL FCFCOF SCCTL SCCT2 SCCT3 SDCTL AGCCTL AGCATT AGC1 AGC2 AGC3 AGC4 AGC5 FCTL FCMD FDATA FPTR SPSCTL RTC1 RTC2 DOUT0 DOUT1 DOUT2 DOUT3 DIN DDIR Minimal Signal Level for Line Echo Cancellation ............... 126 Externally Provided Attenuation ......................................... 127 Margin for Double Talk Detection....................................... 128 DTMF Detector Control ...................................................... 129 DTMF Detector Signal Twist .............................................. 130 DTMF Detector Minimum Signal Level............................... 131 Equalizer Control................................................................ 132 Equalizer Coefficient Data.................................................. 134 Speech Coder Control........................................................ 135 Speech Coder Control 2..................................................... 136 Speech Coder Control 3..................................................... 137 Speech Decoder Control .................................................... 138 AGC Control ....................................................................... 139 Automatic Gain Control Attenuation ................................... 140 Automatic Gain Control 1 ................................................... 141 Automatic Gain Control 2 ................................................... 142 Automatic Gain Control 3 ................................................... 143 Automatic Gain Control 4 ................................................... 144 Automatic Gain Control 5 ................................................... 145 File Control ......................................................................... 146 File Command .................................................................... 147 File Data ............................................................................. 149 File Pointer ......................................................................... 150 SPS Control........................................................................ 151 Real Time Clock 1 .............................................................. 152 Real Time Clock 2 .............................................................. 153 Data Out (Timeslot 0) ......................................................... 154 Data Out (Timeslot 1) ......................................................... 155 Data Out (Timeslot 2) ......................................................... 156 Data Out (Timeslot 3 or Static Mode)................................. 157 Data In (Timeslot 3 or Static Mode).................................... 158 Data Direction (Timeslot 3 or Static Mode) ........................ 159 Note: Registers CCTL, FCTL, FCMD, FDATA, FPTR, RTC1, RTC2, DOUT0, DOUT1, DOUT2, DOUT3 and DDIR are only affected by reset, not by wakeup. For register SPSCTL see the register description for the exact behaviour. 3.3.2 Register Naming Conventions Several registers contain one or more fields for input signal selection. All fields labelled I1 (I2, I3) are five bits wide and use the same coding as shown in table 73. Semiconductor Group 94 11.97 PSB 2168 Detailed Register Description Table 73 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 Signal Encoding 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Signal Description S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 Silence Reserved Reserved Reserved Reserved Serial interface input, channel 1 Serial interface output, channel 1 Serial interface input, channel 2 Serial interface output, channel 2 DTMF generator output DTMF generator auxiliary output Reserved Reserved Speech decoder output Universal attenuator output Line echo canceller output AGC unit output (after AGC) AGC unit output (before AGC) Equalizer output reserved reserved reserved Semiconductor Group 95 11.97 PSB 2168 Detailed Register Description 00h 15 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 REV Revision 0 0 The revision register can only be read. For the PSB 2168, V2.1, all bits except bit 13 are zero. Note: A write access to the revision register does not alter its content. It does, however, reset the ABT bit of the STATUS register. Semiconductor Group 96 11.97 PSB 2168 Detailed Register Description 01h R CCTL 15 0 0 0 0 MV 0 0 PD 0 0 0 MQ MT CS9 Chip Control 0 SAS Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MV Voice Prompt Directory 0: not available 1: available (within EPROM or Flash) PD Power Down 0: PSB 2168 is in active mode 1: enter power-down mode MQ Memory Quality 0: ARAM 1: DRAM MT Memory Type 3 0 1 2 0 1 Description ARAM/DRAM Samsung flash memory CS9 CAS selection 0: other memory 1: 256kx4 or 512kx8 memory SAS Split Address Space 0: other ARAM/DRAM 1: two 2Mx8 devices Semiconductor Group 97 11.97 PSB 2168 Detailed Register Description 02h R INTM 15 RDY 1 0 0 CIA CD CPT CNG SD 0 BSY DTV ATV 0 0 Interrupt Mask Register 0 0 Reset Value 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 If a bit of this register is reset (set to 0), the corresponding bit of the status register does not generate an interrupt. If a bit is set (set to 1), an external interrupt can be generated by the corresponding bit of the status register. l Semiconductor Group 98 11.97 PSB 2168 Detailed Register Description 0Ah R SDCONF 15 0 0 NTS 0 0 0 0 0 DCL 0 Serial Data Interface Configuration 0 EN Reset Value 0 0 0 0 0 0 0 0 0 0 0 NTS Number of Timeslots 13 0 0 ... 1 12 0 0 ... 1 11 0 0 ... 1 10 0 0 ... 1 9 0 0 ... 1 8 0 1 ... 1 Description 1 2 ... 64 DCL Double Clock Mode 0: Single Clock Mode 1: Double Clock Mode EN Enable Interface 0: Interface is disabled (both channels) 1: Interface is enabled (depending on separate channel enable bits) Semiconductor Group 99 11.97 PSB 2168 Detailed Register Description 0Bh R SDCHN1 15 NAS 0 0 PCD EN PCM DD TS Serial Data Interface Channel 1 0 Reset Value 0 0 0 0 0 0 0 0 NAS Number of active DRST strobe (SSDI interface mode) 15 0 ... 1 14 0 ... 1 13 0 ... 1 12 0 ... 1 Description 1 ... 16 PCD PCM Code 0: A-law 1: -law EN Enable Interface 0: Interface is disabled 1: Interface is enabled if SDCONF:EN=1 PCM PCM Mode 0: 16 Bit Linear Coding (two timeslots) 1: 8 Bit PCM Coding (one timeslot) DD Data Direction 0: DD: Data Downstream, DU: Data Upstream 1: DD: Data Upstream, DU: Data Downstream TS Timeslot for Channel 1 5 0 ... 1 4 0 ... 1 3 0 ... 1 2 0 ... 1 1 0 ... 1 0 0 ... 1 Description 0 ... 63 Semiconductor Group 100 11.97 PSB 2168 Detailed Register Description Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case. Semiconductor Group 101 11.97 PSB 2168 Detailed Register Description 0Ch R IFS3 15 HP I1 I2 I3 Interface Select 3 0 Reset Value 0 0 0 0 HP High-Pass for S5 0: Disabled 1: Enabled I1 I2 I3 Input signal 1 for S6 Input signal 2 for S6 Input signal 3 for S6 Note: As all sources are always active, unused sources must be set to 0 (S0). Semiconductor Group 102 11.97 PSB 2168 Detailed Register Description 0Dh R SDCHN2 15 0 0 0 0 0 0 PCD EN PCM DD TS Serial Data Interface Channel 2 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 PCD PCM Code 0: A-law 1: -law EN Enable Interface 0: Interface is disabled 1: Interface is enabled if SDCONF:EN=1 PCM PCM Mode 0: 16 Bit Linear Coding (two timeslots) 1: 8 Bit PCM Coding (one timeslot) DD Data Direction 0: DD: Data Downstream, DU: Data Upstream 1: DD: Data Upstream, DD: Data Downstream TS Timeslot for Channel 2 5 0 0 ... 1 4 0 0 ... 1 3 0 0 ... 1 2 0 0 ... 1 1 0 0 ... 1 0 0 1 ... 1 Description 0 1 ... 63 Note: If PCM=0 then TS denotes the first timeslot of the two consecutive timeslots used. Only even timeslots are allowed in this case. Semiconductor Group 103 11.97 PSB 2168 Detailed Register Description 0Eh R IFS4 15 HP I1 I2 I3 Interface Select 4 0 Reset Value 0 0 0 0 HP High-Pass for S7 0: Disabled 1: Enabled I1 I2 I3 Input signal 1 for S8 Input signal 2 for S8 Input signal 3 for S8 As all sources are always active, unused sources must be set to 0 (S0). Semiconductor Group 104 11.97 PSB 2168 Detailed Register Description 0Fh R IFG5 15 ATT1 1) Interface Gain 5 0 ATT2 1) Reset Value 255 (0 dB) 1) 255 (0 dB) Can be changed on the fly. ATT1 Attenuation for I3 (Channel 1) In order to obtain an attenuation A the parameter ATT1 can be calculated by the following formula: ATT1 = 256 x10 ATT2 Attenuation for I3 (Channel 2) A 20 dB In order to obtain an attenuation A the parameter ATT2 can be calculated by the following formula: ATT2 = 256 x10 A 20 dB Semiconductor Group 105 11.97 PSB 2168 Detailed Register Description 10h R UA 15 ATT 1) Universal Attenuator 0 0 0 0 I1 Reset Value 0 (-100 dB) 1) 0 0 0 0 Can be changed on the fly. ATT Attenuation for UA For a given attenuation A [dB] the parameter ATT can be calculated by the following formula: ATT = 256 x10 I1 Input Selection for UA A 20 dB Semiconductor Group 106 11.97 PSB 2168 Detailed Register Description 11h R DGCTL 15 EN MD 0 0 0 0 0 0 0 0 0 0 DTC DTMF Generator Control 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 EN Generator Enable 0: Disabled 1: Enabled MD Mode 0: raw 1: cooked DTC Dial Tone Code (cooked mode) 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Digit 1 2 3 A 4 5 6 B 7 8 9 C * 0 # D Frequency 697/1209 697/1336 697/1477 697/1633 770/1209 770/1336 770/1477 770/1633 852/1209 852/1336 852/1477 852/1633 941/1209 941/1336 941/1477 941/1633 Semiconductor Group 107 11.97 PSB 2168 Detailed Register Description 12h 15 0 FRQ DGF1 DTMF Generator Frequency 1 0 FRQ Frequency of Generator 1 The parameter FRQ for a given frequency f [Hz] can be calculated by the following formula: f FRQ = 32768 x -----------------4000Hz Semiconductor Group 108 11.97 PSB 2168 Detailed Register Description 13h 15 0 FRQ DGF2 DTMF Generator Frequency 2 0 FRQ Frequency of Generator 2 he parameter FRQ for a given frequency f [Hz] can be calculated by the following formula: f FRQ = 32768 x -----------------4000Hz Semiconductor Group 109 11.97 PSB 2168 Detailed Register Description 14h 15 0 LEV2 0 LEV1 DGL DTMF Generator Level 0 LEV2 Signal Level of Generator 2 In order to obtain a signal level L (relative to the PCM maximum value) for generator 2 the value of LEV2 can be calculated according to the following formula: LEV2 = 128 x10 L 20 dB LEV1 Signal Level of Generator 1 In order to obtain a signal level L (relative to the PCM maximum value) for generator 1 the value of LEV1 can be calculated according to the following formula: LEV1 = 128 x10 L 20 dB Semiconductor Group 110 11.97 PSB 2168 Detailed Register Description 15h 15 ATT2 ATT1 DGATT DTMF Generator Attenuation 0 ATT2 Attenuation of Signal S10 128 + 1024 x10 ATT2 = A 20 dB 128 x10 A 20 dB In order to obtain attenuation A the parameter ATT2 can be calculated by the formula: ;A > 18, 1 dB ;A < 18, 1 dB ATT1 Attenuation of Signal S9 128 + 1024 x10 ATT1 = A 20 dB 128 x10 A 20 dB In order to obtain attenuation A the parameter ATT1 can be calculated by the formula: ;A > 18, 1 dB ;A < 18, 1 dB Semiconductor Group 111 11.97 PSB 2168 Detailed Register Description 16h R CNGCTL 15 EN 0 0 0 0 0 0 0 0 0 0 I1 Calling Tone Control 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 EN Enable 0: CNG unit disabled 1: CNG unit enabled I1 Input Selection for Calling Tone Detector Semiconductor Group 112 11.97 PSB 2168 Detailed Register Description 17h 15 0 TIME CNGBT CNG Burst Time 0 TIME Minimum Time for Calling Tone In order to obtain the parameter TIME for a minimum time t the following formula can be used: TIME = t 0.125 ms Semiconductor Group 113 11.97 PSB 2168 Detailed Register Description 18h 15 0 0 MIN CNGLEV CNG Minimal Signal Level 0 MIN Minimum Signal Level for Calling Tone In order to obtain the parameter MIN for a minimum signal level L the following formula can be used: MIN = 16384 x10 L 20 dB Semiconductor Group 114 11.97 PSB 2168 Detailed Register Description 19h 15 1 1 1 1 RES CNGRES CNG Signal Resolution 0 RES Signal Resolution L 20 dB The parameter RES depends on the noise level L as follows: RES = - 4096 x10 Semiconductor Group 115 11.97 PSB 2168 Detailed Register Description 1Ah R ATDCTL0 15 EN 0 0 I1 0 0 0 0 0 0 ATC Alert Tone Detection 0 0 Reset Value 0 1) 0 0 0 0 0 0 0 0 0 -1) undefined EN Enable alert tone detection 0: The alert tone detection is disabled 1: The alert tone detection is enabled I1 ATC Input signal selection Alert Tone Code 1 0 0 1 1 0 0 1 0 1 Description no tone 2130 2750 2130/2750 Semiconductor Group 116 11.97 PSB 2168 Detailed Register Description 1Bh 15 MD 0 0 DEV 0 0 0 0 MIN ATDCTL1 Alert Tone Detection 1 0 MD Alert tone detection mode 0: Only dual tones will be detected 1: Either dual or single tones will be detected DEV Maximum frequency deviation for alert tone 0: 0.5% 1: 1.1% MIN Minimum level of alert tone signal min 20 dB For a minimum signal level min the parameter MIN is given by the following formula: MIN = 2560 x10 Semiconductor Group 117 11.97 PSB 2168 Detailed Register Description 1Ch R CIDCTL0 15 EN 0 0 I1 DATA Caller ID Control 0 0 Reset Value 0 0 0 0 0 EN CID Enable 0: Disabled 1: Enabled I1 DATA Input signal selection Last received data byte Semiconductor Group 118 11.97 PSB 2168 Detailed Register Description 1Dh 15 NMB NMSS MIN CIDCTL1 Caller ID Control 1 0 NMB Minimum Number of Mark Bits 15 0 0 ... 1 14 0 0 ... 1 13 0 0 ... 1 ... 1 ... 1 12 0 11 0 10 0 1 ... 1 Description 0 10 ... 630 NMSS Minimum Number of Mark/Space Sequences 9 0 0 ... 1 8 0 0 ... 1 7 0 0 ... 1 6 0 0 ... 1 5 0 1 ... 1 311 Description 1 11 MIN Minimum Signal Level for CID Decoder min 20 dB For a minimum signal level min the parameter MIN is given by the following formula: MIN = 640 x10 Semiconductor Group 119 11.97 PSB 2168 Detailed Register Description 20h R CPTCTL 15 EN MD 0 0 0 0 0 0 0 0 0 I1 Call Progress Tone Control 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 EN CPT Detector Enable 0: Disabled 1: Enabled MD CPT Mode 0: raw 1: cooked I1 Input signal selection Semiconductor Group 120 11.97 PSB 2168 Detailed Register Description 21h 15 NUM 0 SN MIN CPTTR Call Progress Tone Thresholds 0 NUM Number of Cycles 15 0 0 ... 1 14 0 0 ... 1 13 0 1 ... 1 cooked mode reserved 2 ... 8 raw mode 0 reserved reserved reserved SN Minimal Signal-to-Noise Ratio 11 1 1 0 0 0 10 1 0 1 0 0 9 1 0 0 1 0 8 1 0 0 0 0 Description 9 dB 12 dB 15 dB 18 dB 22 dB MIN Minimum Signal Level for CPT Detector Value 89h 85h 80h 9Ah 95h 90h Description -40 dB -42 dB -44 dB -46 dB -48 dB -50 dB Semiconductor Group 121 11.97 PSB 2168 Detailed Register Description 22h 15 MINB MING CPTMN CPT Minimum Times 0 MINB Minimum Time for CPT Burst The parameter MINB for a minimal burst time TBmin can be calculated by the following formula: TBmin - 32 ms MINB = ------------------------------------4 MING Minimum Time for CPT Gap The parameter MING for a minimal burst time TGmin can be calculated by the following formula: TGmin - 32 ms MING = ------------------------------------4 Semiconductor Group 122 11.97 PSB 2168 Detailed Register Description 23h 15 MAXB MAXG CPTMX CPT Maximum Times 0 MAXB Maximum Time for CPT Burst The parameter MAXB for a maximal burst time of TBmax can be calculated by the following formula: TBmax - TBmin MAXB = ---------------------------------------8 MAXG Maximum Time for CPT Gap The parameter MAXG for a maximal burst time of TGmax can be calculated by the following formula: TGmax - TGmin MAXG = ----------------------------------------8 Semiconductor Group 123 11.97 PSB 2168 Detailed Register Description 24h 15 DIFB DIFG CPTDT CPT Delta Times 0 DIFB Maximum Time Difference between consecutive Bursts The parameter DIFB for a maximal difference of t ms of two burst durations can be calculated by the following formula: t DIFB = ---------2 ms DIFG Maximum Time Difference between consecutive Gaps The parameter DIFG for a maximal difference of t ms of two gap durations can be calculated by the following formula: t DIFG = ---------2 ms Semiconductor Group 124 11.97 PSB 2168 Detailed Register Description 25h R LECCTL 15 EN MD 0 0 0 0 I1 I2 Line Echo Cancellation Control 0 Reset Value 0 0 0 0 0 0 0 0 EN Enable 0: Disabled 1: Enabled MD Mode 0: Normal 1: Extended I1 I2 Input signal selection for I1 Input signal selection for I2 Semiconductor Group 125 11.97 PSB 2168 Detailed Register Description 26h 15 0 MIN LECLEV Minimal Signal Level for Line Echo Cancellation 0 MIN The parameter MIN for a minimal signal level L (dB) can be calculated by the following formula: 512 x ( 96.3 + L ) MIN = --------------------------------------5 x log2 Semiconductor Group 126 11.97 PSB 2168 Detailed Register Description 27h 15 0 ATT LECATT Externally Provided Attenuation 0 ATT The parameter ATT for an externally provided attenuation A (dB) can be calculated by the following formula: 512 x A ATT = ------------------5 x log2 Semiconductor Group 127 11.97 PSB 2168 Detailed Register Description 28h 15 0 MGN LECMGN Margin for Double Talk Detection 0 MGN The parameter MGN for a margin of L (dB) can be calculated by the following formula: 512 x L MGN = ------------------5 x log2 Semiconductor Group 128 11.97 PSB 2168 Detailed Register Description 29h R DDCTL 15 EN 0 0 I1 0 0 0 DTC DTMF Detector Control 0 Reset Value 0 1) 0 0 0 0 0 0 -1) undefined EN Enable DTMF tone detection 0: The DTMF detection is disabled 1: The DTMF detection is enabled I1 DTC Input signal selection DTMF Tone Code 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency 941 / 1633 697 / 1209 697 / 1336 697 / 1477 770 / 1209 770 / 1336 770 / 1477 852 / 1209 852 / 1336 852 / 1477 941 / 1336 941 / 1209 941 / 1477 697 / 1633 770 / 1633 852 / 1633 Digit D 1 2 3 4 5 6 7 8 9 0 * # A B C Semiconductor Group 129 11.97 PSB 2168 Detailed Register Description 2Ah 15 0 TWIST DDTW DTMF Detector Signal Twist 0 TWIST Signal twist for DTMF tone In order to obtain a minimal signal twist T the parameter TWIST can be calculated by the following formula: TWIST = 32768 x10 ( 0.5 dB - T ) 10 dB Note: TWIST must be in the range [4096,20480] Semiconductor Group 130 11.97 PSB 2168 Detailed Register Description 2Bh 15 1 1 1 1 1 1 1 1 1 1 MIN DDLEV DTMF Detector Minimum Signal Level 0 MIN Minimum Signal Level 5 0 0 ... 1 1 4 0 0 ... 0 0 3 1 1 ... 0 0 2 1 1 ... 0 0 1 1 1 ... 0 1 0 0 1 ... 1 0 Description -50 dB -49 dB ... -31 dB -30 dB Note: Values outside the given range are reserved and must not be used. Semiconductor Group 131 11.97 PSB 2168 Detailed Register Description 2Eh R FCFCTL 15 EN 0 ADR 0 0 0 I Equalizer Control 0 Reset Value 0 0 0 0 0 0 0 EN Enable equalizer 0: The equalizer is disabled 1: The equalizer is enabled ADR Coefficient address 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Coefficient A1 A2 A3 A4 A5 A6 A7 A8 A9 B2 B3 B4 B5 B6 B7 B8 B9 C1 D1 D2 D3 D4 D5 Semiconductor Group 132 11.97 PSB 2168 Detailed Register Description 13 0 0 0 0 0 0 0 0 0 1 1 1 1 12 1 1 1 1 1 1 1 1 1 0 0 0 0 11 0 1 1 1 1 1 1 1 1 0 0 0 0 10 1 0 0 0 0 1 1 1 1 0 0 0 0 9 1 0 0 1 1 0 0 1 1 0 0 1 1 8 1 0 1 0 1 0 1 0 1 0 1 0 1 Coefficient D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 C2 I1 Input signal selection Semiconductor Group 133 11.97 PSB 2168 Detailed Register Description 2Fh 15 V FCFCOF Equalizer Coefficient Data 0 V Coefficient value For the coefficient A1-A9, B2-B9 and D1-D17 the following formula can be used to calculate V for a coefficient c: V = 32768 x c ; -1 c < 1 For the coefficients C1 and C2 the following formula can be used to calculate V for a coefficient c: V = 128 x c ; 1 c < 256 Semiconductor Group 134 11.97 PSB 2168 Detailed Register Description 30h R SCCTL 15 EN HQ 1) Speech Coder Control 0 VC 0 0 0 I1 I2 Reset Value 0 1) 0 0 0 0 0 0 0 Can be changed on the fly. EN Enable 0: Disabled 1: Enabled HQ High Quality Mode 0: Long Play Mode 1: High Quality Mode VC Voice Controlled Start of Recording 0: Disabled 1: Enabled I1 I2 Input signal selection (first input) Input signal selection (second input) Semiconductor Group 135 11.97 PSB 2168 Detailed Register Description 31h 15 TIME MIN SCCT2 Speech Coder Control 2 0 TIME The parameter TIME for a time t ([ms]) can be calculated by the following formula: t TIME = ----32 MIN The parameter MIN for a signal level L ([dB]) can be calculated by the following formula: MIN = 16384 x10 L ----20 Semiconductor Group 136 11.97 PSB 2168 Detailed Register Description 32h 15 0 LP 0 0 0 0 0 0 0 SCCT3 Speech Coder Control 3 0 0 LP The parameter LP for a time constant of t ([ms]) can be calculated by the following formula: 256 LP = -------t Semiconductor Group 137 11.97 PSB 2168 Detailed Register Description 34h R SDCTL 15 EN 0 0 0 0 0 0 0 0 0 0 0 0 Speech Decoder Control 0 SPEED Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN Enable 0: Disabled 1: Enabled SPEED Playback Speed 1 0 0 1 1 0 0 1 0 1 Description normal speed 0.5 times normal speed 1.5 times normal speed 2.0 times normal speed Semiconductor Group 138 11.97 PSB 2168 Detailed Register Description 38h R AGCCTL 15 EN 0 0 0 0 0 I1 I2 AGC Control 0 Reset Value 0 0 0 0 0 0 0 0 EN Enable 0: Disabled 1: Enabled I1 I2 Input signal selection for I1 Input signal selection for I2 Semiconductor Group 139 11.97 PSB 2168 Detailed Register Description 39h R AGCATT 15 ATT Automatic Gain Control Attenuation 0 Reset Value 0 (-100 dB) ATT The parameter ATT for an attenuation A ([dB]) can be calculated by the following formula: A ----20 ATT = 32768 x10 Semiconductor Group 140 11.97 PSB 2168 Detailed Register Description 3Ah 15 COM AG_INIT AGC1 Automatic Gain Control 1 0 COM The parameter COM for a signal level L ([dB]) can be calculated by the following formula: ----------------------- 128 + 10 20 COM = L + 42, 14 -----------------------10 20 L + 66, 22 ;L < -42,14 dB ;L > -42,14 dB AG_INIT In order to obtain an initial gain G ([db]) the parameter AG_INIT can be calculated by the following formula: G + 18, 06 ----------------------- ;G < 24 dB 128 + 10 20 AG_INIT = G - 6, 02 --------------------;G > 24 dB 10 20 Semiconductor Group 141 11.97 PSB 2168 Detailed Register Description 3Bh 15 SPEEDL SPEEDH AGC2 Automatic Gain Control 2 0 SPEEDL This parameter has no dimension. It controls the regulation speed of the AGC for signal levels below the comparator threshold (AGC1:COM). The higher the value the faster the AGC. Setting this parameter to 0 inhibits regulation. SPEEDH This parameter has no dimension. It controls the regulation speed of the AGC for signal levels above the comparator threshold (AGC1:COM). The higher the value the faster the AGC. Setting this parameter to 0 inhibits regulation. Semiconductor Group 142 11.97 PSB 2168 Detailed Register Description 3Ch 15 MIN MAX AGC3 Automatic Gain Control 3 0 MIN The parameter MIN for a gain G ([dB]) can be calculated by the following formula: ----------------------- 128 + 10 20 MIN = G - 6, 02 --------------------10 20 G + 18, 06 ;G < 24 dB ;G > 24 dB MAX The parameter MAX for an attenuation A ([dB]) can be calculated by the following formula: MAX = A + 42, 14 -----------------------10 20 Semiconductor Group 143 11.97 PSB 2168 Detailed Register Description 3Dh 15 DEC LIM AGC4 Automatic Gain Control 4 0 DEC The parameter DEC for a time constant t ([1/ms]) is given by the following formula: 256 DEC = -------t LIM The parameter LIM for a signal level L ([dB]) can be calculated by the following formula: -------------------- 128 + 10 20 LIM = L + 66, 22 -----------------------10 20 L + 90, 3 ;L < 66,22 dB ;L > 66,22 dB Semiconductor Group 144 11.97 PSB 2168 Detailed Register Description 3Eh 15 0 0 0 0 0 0 0 0 1 LP AGC5 Automatic Gain Control 5 0 LP The parameter LP for a time constant t ([1/ms]) is given by the following formula: 16 LP = ----t Semiconductor Group 145 11.97 PSB 2168 Detailed Register Description 40h R FCTL 15 0 MD MS TS 0 0 0 0 FNO File Control 0 Reset Value 0 0 0 0 0 0 0 0 0 MD Mode 0: Audio Mode 1: Binary Mode MS Memory Space 0: R/W Memory 1: Voice Prompt Directory TS Time Stamp 0: no update of RTC1/RTC2 entry of file descriptor 1: RTC1/RTC2 entries are updated by content of RTC1/RTC2 registers. FNO File Number Semiconductor Group 146 11.97 PSB 2168 Detailed Register Description 41h R FCMD 15 0 IN RD 0 0 0 0 0 ABT EIE 0 CMD File Command 0 Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 IN Initialize 0: no 1: yes (if CMD=1111) RD Remap Directory 0: no 1: yes ABT Abort Command 0: no 1: abort recompress EIE Enable Immediate Execution 0: disabled (default, always possible) 1: enabled (restricted to certain commands and operating modes) CMD File Command 4 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 1 1 2 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 Description Open File Activate Seek Cut File Read Data Write Data Memory Status Recompress file Read File Descriptor - User Write File Descriptor - User Semiconductor Group 147 11.97 PSB 2168 Detailed Register Description 4 0 0 0 0 0 0 1 1 1 1 1 1 1 3 1 1 1 1 1 1 0 0 0 0 0 1 1 2 0 0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 Description Read File Descriptor - RTC1 Read File Descriptor - RTC2 Read File Descriptor - LEN Garbage Collection Open Next Free File Initialize DMA Read DMA Write Erase Block Set Address reserved reserved reserved Semiconductor Group 148 11.97 PSB 2168 Detailed Register Description 42h R FDATA 15 FREE File Data 0 Reset Value 0 The FDATA register contains the following information after a memory status command: FREE Free Blocks Number of blocks (1 kByte) currently usable for recording. Semiconductor Group 149 11.97 PSB 2168 Detailed Register Description 43h R FPTR 15 File Pointer 0 0 0 0 0 Phrase selector File Pointer 0 Reset Value 0 Semiconductor Group 150 11.97 PSB 2168 Detailed Register Description 47h R SPSCTL 15 POS 0 0 0 0 0 0 0 MODE SP1 SPS Control 0 SP0 Reset Value 0 1) 0 0 0 0 0 0 0 0 -1) -1) undefined POS Position of Status Register Window 15 0 0 ... 1 14 0 0 ... 1 13 0 0 ... 1 12 0 1 ... 0 SPS0 Bit 0 Bit 1 ... Bit 14 SPS1 Bit 1 Bit 2 ... Bit 15 MODE Mode of SPS Interface 4 0 0 1 1 3 0 0 0 1 2 0 1 1 0 Description Disabled (SPS0 and SPS1 zero) Output of SP1 and SP0 Expanded address output Output of STATUS register SP1 Direct Control for SPS1 0: SPS1 set to 0 1: SPS1 set to 1 SP0 Direct Control for SPS0 0: SPS0 set to 0 1: SPS0 set to 1 Note: If mode 1 has been selected prior to power-down, both mode 1 and the values of SP1 and SP0 are retained during power-down and wake-up. Other modes are reset to 0 during power down. Semiconductor Group 151 11.97 PSB 2168 Detailed Register Description 48h R RTC1 15 0 0 0 0 MIN SEC Real Time Clock 1 0 Reset Value 0 0 0 0 0 0 MIN Minutes Number of minutes elapsed in the current hour (0-59). SEC Seconds Number of seconds elapsed in the current minute (0-59). Semiconductor Group 152 11.97 PSB 2168 Detailed Register Description 49h R RTC2 15 DAY HR Real Time Clock 2 0 Reset Value 0 0 DAY Days Number of days elapsed since last reset (0-2047). HR Hours Number of hours elapsed in the current day (0-23). Semiconductor Group 153 11.97 PSB 2168 Detailed Register Description 4Ah R DOUT0 15 0 0 0 0 DATA Data Out (Timeslot 0) 0 Reset Value 0 0 0 0 0 DATA Output Data Output data for pins MA0-MA11 while MA12=1 (only if HWCONFIG1:APP=10). Note: This register cannot be read. Semiconductor Group 154 11.97 PSB 2168 Detailed Register Description 4Bh R DOUT1 15 0 0 0 0 DATA Data Out (Timeslot 1) 0 Reset Value 0 0 0 0 0 DATA Output Data Output data for pins MA0-MA11 while MA13=1 (only if HWCONFIG1:APP=10). Note: This register cannot be read. Semiconductor Group 155 11.97 PSB 2168 Detailed Register Description 4Ch R DOUT2 15 0 0 0 0 DATA Data Out (Timeslot 2) 0 Reset Value 0 0 0 0 0 DATA Output Data Output data for pins MA0-MA11 while MA14=1 (only if HWCONFIG1:APP=10). Note: This register cannot be read. Semiconductor Group 156 11.97 PSB 2168 Detailed Register Description 4Dh R DOUT3 15 DATA Data Out (Timeslot 3 or Static Mode) 0 Reset Value 0 DATA Output Data Output data for pins MA0-MA11 while MA15=1 (only if HWCONFIG1:APP=10). Output data for pins MA0-MA15 (only if HWCONFIG1:APP=01) Note: This register cannot be read. Semiconductor Group 157 11.97 PSB 2168 Detailed Register Description 4Eh 15 DATA DIN Data In (Timeslot 3 or Static Mode) 0 DATA Input Data Input data for pins MA0-MA11 at falling edge of MA12 (only if HWCONFIG1:APP=10). Input data for pins MA0-MA15 (only if HWCONFIG1:APP=01) Semiconductor Group 158 11.97 PSB 2168 Detailed Register Description 4Fh R DDIR 15 DIR Data Direction (Timeslot 3 or Static Mode) 0 Reset Value 0 (all inputs) DIR 0: input Port Direction Port direction during MA12=1 or in static mode. 1: output Note: This register cannot be read. Semiconductor Group 159 11.97 PSB 2168 Electrical Characteristics 4 Electrical Characteristics Electrical Characteristics Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values Unit 4.1 Parameter Ambient temperature under bias Storage temperature Supply Voltage Supply Voltage Supply Voltage Voltage of pin with respect to ground: XTAL1, XTAL2 Voltage on any pin with respect to ground TA TSTG VDD VDDA VDDP VS VS -20 to 85 - 65 to125 -0.5 to 4.2 -0.5 to 4.2 -0.5 to 6 0 to VDDA If VDDP < 3 V: - 0.4 to VDD + 0.5 If VDDP > 3 V: - 0.4 to VDDP + 0.5 C C V V V V V ESD integrity (according MIL-Std. 883D, method 3015.7): 2 kV Exception: The pins INT, SDX, DU/DX, DD/DR, SPS0, SPS1 and MD0-MD7 are not protected against voltage stress >1 kV. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 4.2 DC Characteristics VDD/VDDA = 3.3 V 0.3 V; VDDP = 5 V 10%; VSS/VSSA = 0 V; TA = 0 to 70 C Parameter Input leakage current H-input level (except MA0-MA15, XTAL1,OSC1) H-input level (OSC1) Symbol min. IIL VIH1 VIH2 - 1.0 2.0 0.8 VDD 2.0 - 0.3 Limit Values typ. max. 1.0 VDDP + 0.3 VDDA + 0.3 VDD 0.8 A V V V V 0 V VIN VDD Unit Test Condition H-input level (MA0-MA15, MCTL1)) VIH3 L-input level (except pins XTAL1,OSC1) Semiconductor Group VIL1 160 11.97 PSB 2168 Electrical Characteristics VDD/VDDA = 3.3 V 0.3 V; VDDP = 5 V 10%; VSS/VSSA = 0 V; TA = 0 to 70 C Parameter L-input level (OSC1) H-output level (except DU/DX, DD/DR, MA0-MA15, SPS0, SPS1, MD0-MD7) Symbol min. VIL2 VOH1 - 0.3 VDD - 0.45 VDD - 0.6 VDD - 0.45 VDD - 0.6 0.45 0.45 50 25 150 65 240 120 0.45 350 750 1300 10 15 10 20 55 1 50 70 70 10 Limit Values typ. max. 0.2 VDDA V V IO = 2 mA Unit Test Condition H-output level (SPS0, SPS1, MD0- VOH2 MD7, SDX, INT) H-output level (MA0-MA15) H-output level (DU/DX, DD/DR) L-output level (except DU/DX, DD/DR, MA0-MA15) L-output level (MA0-MA15) (address mode or APP output) L-output current (MA0-MA15) (after reset) H-output current (MCTL1)) L-output level (pins DU/DX, DD/ DR) Internal pullup current (FRDY) Input capacitance Output capacitance VOH3 VOH4 VOL1 VOL2 ILO IHO VOL3 ILI CI CO V V V V V A A V A pF pF A A mA A IO = 2 mA IO = 5 mA IO = 7 mA IO = - 2 mA IO = - 5 mA RST=1 RST=1 IO = - 7 mA IDDS1 VDD supply current (power down, no refresh, no RTC) VDD supply current (power down, refresh, RTC) VDD supply current operating VDDP supply current 1) IDDS2 IDDO IDDP VDD = 3.3 V MCTL signals are (W/FWE, VPRD/FCLE, RAS/FOE, CAS0/ALE, CAS1/FCS) Semiconductor Group 161 11.97 PSB 2168 Electrical Characteristics 4.3 AC Characteristics Digital inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The ACtesting input/output waveforms are shown below. Figure 55 Input/Output Waveforms for AC-Tests Semiconductor Group 162 11.97 PSB 2168 Electrical Characteristics DTMF Detector Parameter Frequency deviation accept Frequency deviation reject Acceptance level Rejection level Twist deviation accept Noise Tolerance Signal duration accept Signal duration reject Gap duration accept 18 40 23 +/-2 Symbol min. -1.5 3.5 -45 Limit Values typ. max. 1.5 -3.5 0 -50 +/-8 12 % % dB dB dB dB ms ms ms rel. to max. PCM rel. to max. PCM programmable Unit Test Condition CPT Detector Parameter Frequency acceptance range Frequency rejection range Acceptance level Rejection level Signal duration accept Signal duration reject 50 10 Symbol min. 300 800 -45 Limit Values typ. max. 640 200 0 -50 Hz Hz dB dB ms ms rel. to max. PCM rel. to max. PCM programmable Unit Test Condition Caller ID Decoder Parameter Frequency deviation accept Acceptance level Transmission rate Noise Tolerance Symbol min. -2 -45 1188 1200 Limit Values typ. max. 2 0 1212 -12 % dB baud dB rel. to max. PCM Unit Test Condition Semiconductor Group 163 11.97 PSB 2168 Electrical Characteristics Alert Tone Detector Parameter Frequency deviation accept Frequency deviation accept Frequency deviation reject Acceptance level Rejection level Twist deviation accept Noise Tolerance Signal duration accept Gap duration accept 75 40 Symbol min. -0.5 -1.1 3.5 -40 Limit Values typ. max. 0.5 1.1 -3.5 0 -5 +/-7 20 % % % dB dB dB dB ms ms rel. to max. PCM rel. to acceptance level ATDCTL1:DEV=0 ATDCTL1:DEV=1 Unit Test Condition CNG Detector Parameter Frequency deviation accept Frequency deviation reject Acceptance level Acceptance level Rejection level Signal duration reject Symbol min. -40 -50 -45 -50 -3 dB -1 Limit Values typ. max. 40 50 0 0 Hz Hz dB dB dB % SNR >10 dB SNR >15 dB rel. to CNGLEV:MIN rel. to CNGBT:TIME Unit Test Condition Semiconductor Group 164 11.97 PSB 2168 Electrical Characteristics Status Register Update Time The individual bits of the STATUS register may change due to an event (like a recognized DTMF tone) or a command. The timing can be divided into four classes Table 74 Class Min. I A D E 1) Status Register Update Timing Timing Max. 0 125 s1) 250 s Immediately after command has been issued Command has been accepted Deactivation time after command has been issued Associated event has happened 0 0 125 S Comment one FSC period With these definitions the timing of the individual bits in the STATUS register can be given as shown in table: Bit 0->1 1->0 1) Timing Diagrams RDY A I ABT E A CIA E A,D CD E E,D CPT E E,D CNG E D SD E E,D ERR E A BSY A1) E DTV E E,D ATV E E,D up to 30 ms if command is either SDCTL:EN=1 or SCCTL:EN=1 Semiconductor Group 165 11.97 PSB 2168 Electrical Characteristics CL1 XTAL1 CL2 OSC1 X1 CL1 XTAL2 CL2 X2 OSC2 Figure 56 Oscillator Circuits Recommended Values Oscillator Circuits Load CL1 Static capacitance X1 Motional capacitance X1 Resonance resistor X1 Load CL2 Static Capacitance X2 Motional capacitance X2 Resonance resistor X2 Frequency deviation 1.7 3.5 18 40 100 Value Min Typ 5 17 60 30 Max 40 pF pF fF pF pF fF k ppm Unit Semiconductor Group 166 11.97 PSB 2168 Electrical Characteristics t1 t2 DCL t3 t4 DD/DR t5 DU/DX first bit last bit t6 t7 DU/DX bit n bit n+1 t8 Figure 57 SSDI/IOM(R)-2 Interface - Bit Synchronization Timing DCL t9 FSC t10 t9 t10 Figure 58 SSDI/IOM(R)-2 Interface - Frame Synchronization Timing Parameter SSDI/IOM(R)-2 Interface DCL period DCL high DCL low Input data setup Symbol t1 t2 t3 t4 Limit values Min 90 35 35 20 Max ns ns ns ns Unit Semiconductor Group 167 11.97 PSB 2168 Electrical Characteristics Parameter SSDI/IOM(R)-2 Interface Input data hold Output data from high impedance to active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC setup FSC hold FSC jitter (deviation per frame) Symbol t5 t6 t7 t8 t9 t10 40 40 -200 200 Limit values Min 20 30 30 30 Max ns ns ns ns ns ns ns Unit Semiconductor Group 168 11.97 PSB 2168 Electrical Characteristics DCL t1 DXST t2 DRST t3 t4 t5 t6 FSC t7 Figure 59 SSDI Interface - Strobe Timing Parameter SSDI Interface DXST delay DRST inactive setup DRST inactive hold DRST active setup DRST active hold FSC setup FSC hold Symbol t1 t2 t3 t4 t5 t6 t7 20 20 20 20 8 40 Limit values Min Max 20 ns ns ns ns ns DCL cycles ns Unit Semiconductor Group 169 11.97 PSB 2168 Electrical Characteristics t1 t4 CS t2 t3 t5 SCLK t6 SDR t7 t8 t11 t9 SDX t10 INT t12 Figure 60 Serial Control Interface Parameter SCI Interface SCLK cycle time SCLK high time SCLK low time CS setup time CS hold time SDR setup time SDR hold time SDX data out delay CS high to SDX tristate SCLK to SDX active SCLK to SDX tristate CS to INT delay Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Limit values Min 500 100 100 40 10 40 40 80 40 80 40 80 Max ns ns ns ns ns ns ns ns ns ns ns ns Unit Semiconductor Group 170 11.97 PSB 2168 Electrical Characteristics t1 t2 AFECLK t3 AFEFS t4 t5 t4 Figure 61 Clock Master Timing Parameter AFE Interface AFECLK period (HWCONFIG3:CM0=0) AFECLK period (HWCONFIG3:CM0=1) AFECLK high AFECLK low AFEFS output delay AFEFS high 1) Symbol Limit values Min t1 13.5*p1)/ fXTAL -10 4.5*p/fXTAL -10 4*1/fXTAL 4*1/fXTAL 30 4*t1 Max Unit 13.5*p/fXTAL ns +10 4.5*p/fXTAL +10 ns t1 t2 t3 t4 t5 ns The factor p is determined by HWCONFIG1:XTAL (see register description) Semiconductor Group 171 11.97 PSB 2168 Electrical Characteristics MA0-MA13 row addr. t1 t2 col. addr. RAS t4 t5 t3 t6 CAS0,CAS1 t7 t8 MD0-MD7 Figure 62 Memory Interface - DRAM Read Access Parameter Memory Interface - DRAM Read Access row address setup time row address hold time column address setup time RAS precharge time RAS to CAS delay CAS pulse width Data input setup time Data input hold time Symbol t1 t2 t3 t4 t5 t6 t7 t8 Limit values Min 50 50 50 110 110 110 40 0 2000 2000 Max ns ns ns ns ns ns ns ns Unit Semiconductor Group 172 11.97 PSB 2168 Electrical Characteristics MA0-MA13 row addr. t1 t2 col. addr. RAS t4 t5 t3 t6 CAS0,CAS1 t9 t10 W t7 t8 MD0-MD7 Figure 63 Memory Interface - DRAM Write Access Parameter Memory Interface - DRAM Write Access row address setup time row address hold time column address setup time RAS precharge time RAS to CAS delay CAS pulse width Data output setup time Data output hold time RAS to W delay W to CAS setup Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Limit values Min 50 50 50 110 110 110 100 50 50 50 2000 2000 Max ns ns ns ns ns ns ns ns ns ns Unit Semiconductor Group 173 11.97 PSB 2168 Electrical Characteristics t1 t2 RAS t3 t4 CAS0,CAS1 Figure 64 Memory Interface - DRAM Refresh Cycle Parameter Memory Interface - DRAM Refresh Cycle RAS precharge time RAS low time CAS setup CAS hold Symbol t1 t2 t3 t4 Limit values Min 100 200 100 100 5000 Max ns ns ns ns Unit Note: The frequency of the DRAM refresh cycle depends on the selected mode. In active mode or normal refresh mode (during power down) the minimal frequency is 64 kHz. In battery backup mode, the refresh frequency is 8 kHz. Semiconductor Group 174 11.97 PSB 2168 Electrical Characteristics MA0-MA15 t1 linear address t2 VPRD t3 t4 MD0-MD7 Figure 65 Memory Interface - EPROM Read Parameter Memory Interface - EPROM Read Address setup before VPRD VPRD low time Data setup time Data hold time Symbol t1 t2 t3 t4 Limit values Min 110 500 40 0 Max ns ns ns ns Unit Semiconductor Group 175 11.97 PSB 2168 Electrical Characteristics MA0-MA11 t1 A16-A23 and FCS0-FCS3 FCS(FCS0-FCS3) t2 FCLE t3 t4 t5 FWR t6 t7 MD0-MD7 Figure 66 Memory Interface - Samsung Command Write Parameter Memory Interface - Samsung Command Write Address setup before FCS, FCLE FCS low time, FCLE high time FWR hold after FCLE rising FWR low time FWR setup before FCLE falling Data setup time Data hold time Symbol Limit values Min t1 t2 t3 t4 t5 t6 t7 100 400 100 200 100 200 50 Max ns ns ns ns ns ns ns Unit Note: FCS stays low if other cycles follow for the same access. Semiconductor Group 176 11.97 PSB 2168 Electrical Characteristics t1 ALE t2 t3 t4 FWR t5 t6 MD0-MD7 Figure 67 Memory Interface - Samsung Address Write Parameter Memory Interface - Samsung Address Write ALE high time FWR hold after ALE rising FWR low time FWR setup before ALE falling Data setup time Data hold time Symbol Limit values Min t1 t2 t3 t4 t5 t6 400 100 200 100 200 50 Max ns ns ns ns ns ns Unit Semiconductor Group 177 11.97 PSB 2168 Electrical Characteristics t1 FWR t2 t3 MD0-MD7 Figure 68 Memory Interface - Samsung Data Write Parameter Memory Interface - Samsung Data Write FWR low time Data setup time Data hold time Symbol t1 t2 t3 Limit values Min 200 200 50 Max ns ns ns Unit Semiconductor Group 178 11.97 PSB 2168 Electrical Characteristics t1 FOE t2 t3 MD0-MD7 Figure 69 Memory Interface - Samsung Data Read Parameter Memory Interface - Samsung Data Read FOE low time Data setup time Data hold time Symbol t1 t2 t3 Limit values Min 200 40 0 Max ns ns ns Unit Semiconductor Group 179 11.97 PSB 2168 Electrical Characteristics t1 t2 MA13 MA12 t3 t4 MA0-MA11 Figure 70 Auxiliary Parallel Port - Multiplex Mode Parameter Auxiliary Port Interface - Multiplex Mode Active time (MA0-MA15) Gap time (MA0-MA15) Data setup time Data hold time Symbol t1 t2 t3 t4 50 0 Limit values Min Typ 2 125 Max ms s ns ns Unit Semiconductor Group 180 11.97 PSB 2168 Electrical Characteristics t1 VDD/VDDP t3 t2 RST t4 Figure 71 Reset Timing Parameter Reset Timing Symbol t1 t2 t3 t4 0 0.1 1000 Limit values Min Max 20 ms ns ms ns Unit VDD/VDDP/VDDA rise time 5%-95% Supply voltages stable to RST high Supply voltages stable to RST low RST high time Semiconductor Group 181 11.97 PSB 2168 Package Outlines 5 Package Outlines Plastic Package, P-MQFP-80 (SMD) (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 182 Dimensions in mm 11.97 PSB 2168 Index A Abort Clearing Event .......................... 63, 96 Functional Description .................... 62 Status Bit ......................................... 87 Alert Tone Detector Electrical Characteristics ............... 164 Functional Description .................... 28 Registers ............................... 116-117 Status Bit ......................................... 88 ARAM see Memory Interface Automatic Gain Control Functional Description .................... 40 Registers ............................... 139-145 Auxiliary Parallel Port Electrical Characteristics ............... 180 Mode Bits ........................................ 90 Multiplex Mode ................................ 85 Registers ............................... 154-159 Static Mode ..................................... 85 Functional Description .................... 29 Registers ............................... 120-124 Status Bit ........................................ 88 D Digital Interface Functional Description .................... 37 Mode Bits ........................................ 90 DRAM see Memory Interface DTMF Detector Electrical Characteristics .............. 163 Functional Description .................... 26 Registers ............................... 129-131 Status Bit ........................................ 88 DTMF Generator Functional Description .................... 33 Registers ............................... 107-111 E EPROM see Memory Interface Equalizer Functional Description .................... 42 Registers ............................... 132-134 Execution Times File Commands ............................... 58 C Caller ID Decoder Electrical Characteristics ............... 163 Functional Description .................... 31 Registers ............................... 118-119 Status Bits ....................................... 87 CNG Detector Electrical Characteristics ............... 164 Functional Description .................... 27 Registers ............................... 112-115 Status Bit ......................................... 88 CPT Detector Electrical Characteristics ............... 163 F File Commands Access File Descriptor ................. 53 Compress .................................... 52 Create Next New ......................... 50 Delete .......................................... 52 Execution Times .......................... 58 11.97 Semiconductor Group 183 PSB 2168 Index New File ....................................... 50 Open ............................................ 50 Read Binary Data ......................... 54 Registers ............................ 146-150 Restrictions .................................. 59 Seek ............................................. 51 Status Bits .................................... 88 Tailcut .......................................... 52 Write Binary Data ......................... 55 Type Audio ............................................ 45 Binary ........................................... 45 Phrase .......................................... 46 User Data Word .............................. 47 Flash Memory see Memory Interface M Memory Interface ARAM/DRAM Connection Diagram .................... 77 Electrical Characteristics ... 172-174 Refresh .................................. 79, 91 Timing .......................................... 78 EPROM Connection Diagram .................... 80 Electrical Characteristics ........... 175 Timing .......................................... 80 Flash Connection Diagram .................... 81 Electrical Characteristics ... 176-179 In-Circuit Programming .......... 76, 91 Multiple Devices ........................... 82 Timing .......................................... 83 Register .......................................... 97 Supported Devices ......................... 76 Memory Management Activation ........................................ 49 Directories ....................................... 44 ExecutionTimes .............................. 58 Files ................................................ 45 Garbage Collection ......................... 53 Initialization ..................................... 48 Memory Status ................................ 53 Overview ......................................... 44 Status .............................................. 46 H Hardware Configuration Functional Description .................... 63 Registers ......................................... 89 I Interrupt Functional Description .................... 61 Pin Configuration ............................ 89 Register ........................................... 98 IOM(R)-2 Interface Electrical Characteristics ....... 167-168 Functional Description .................... 66 see also: Digital Interface O Oscillator Electrical Characteristics .............. 166 Mode Bits ........................................ 90 L Line Echo Canceller Functional Description .................... 24 Registers ............................... 125-128 P Power Down Semiconductor Group 184 11.97 PSB 2168 Index Functional Description ................. 60 Status Bit ......................................... 89 SPS Outputs Functional Description .................... 60 Register ........................................ 151 SSDI Interface Electrical Characteristics ...... 167-169 Functional Description .................... 70 see also: Digital Interface Status Register Definition ......................................... 87 Update Timing .............................. 165 R Real Time Clock Configuration Bits ............................ 89 Functional Description .................... 60 Oscillator ....................................... 166 Registers ............................... 152-153 Recompression ................................... 52 Reset Electrical Characteristics ............... 181 Functional Description .................... 60 Register Values ............................... 93 Restrictions File Commands ............................... 59 Modules .......................................... 64 Revision Functional Description .................... 63 Register ........................................... 96 U Universal Attenuator Functional Description .................... 39 Register ........................................ 106 S Serial Control Interface Command Opcodes ........................ 75 Electrical Characteristics ............... 170 Functional Description .................... 72 Signals Encoding ......................................... 94 Reference Table ............................. 94 Speech Coder Functional Description .................... 34 Registers ............................... 135-137 Speech Decoder Functional Description .................... 36 Register ......................................... 138 Semiconductor Group 185 11.97 |
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